Inventor · disambiguated record
Valavan Manohararajah
Also filed as: MANOHARARAJAH VALAVAN
47 granted patents·3 pending applications·408 citations·filing 2003–2020
98Inventor score
Top patents by PatentIndex Score
50 records- 0198US8588014B1Methods for memory interface calibrationFUNG RYAN·Filed 2011·Granted Nov 19, 2013·36 cites·12 claims
- 0297US8565033B1Methods for calibrating memory interface circuitryMANOHARARAJAH VALAVAN·Filed 2011·Granted Oct 22, 2013·79 cites·20 claims
- 0394US7500216B1Method and apparatus for performing physical synthesis hill-climbing on multi-processor machinesALTERA CORP·Filed 2007·Granted Mar 3, 2009·42 cites·27 claims
- 0492US9660650B1Integrated circuits with improved register circuitryALTERA CORP·Filed 2014·Granted May 23, 2017·11 cites·26 claims
- 0592US9558849B1Methods for memory interface calibrationALTERA CORP·Filed 2013·Granted Jan 31, 2017·9 cites·20 claims
- 0692US8677298B1Programmable device configuration methods adapted to account for retimingALTERA CORP·Filed 2013·Granted Mar 18, 2014·18 cites·26 claims
- 0790US8296696B1Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesisCHIU GORDON RAYMOND·Filed 2008·Granted Oct 23, 2012·24 cites·21 claims
- 0889US8963581B1Pipelined direct drive routing fabricALTERA CORP·Filed 2012·Granted Feb 24, 2015·8 cites·16 claims
- 0988US9553590B1Configuring programmable integrated circuit device resources as processing elementsALTERA CORP·Filed 2012·Granted Jan 24, 2017·11 cites·24 claims
- 1086US8863059B1Integrated circuit device configuration methods adapted to account for retimingALTERA CORP·Filed 2013·Granted Oct 14, 2014·7 cites·24 claims
- 1185US7996797B1Method and apparatus for performing multiple stage physical synthesisALTERA CORP·Filed 2007·Granted Aug 9, 2011·10 cites·32 claims
- 1284US8856702B1Method and apparatus for performing multiple stage physical synthesisALTERA CORP·Filed 2013·Granted Oct 7, 2014·5 cites·21 claims
- 1384US8510688B1Method and apparatus for performing multiple stage physical synthesisSINGH DESHANAND·Filed 2011·Granted Aug 13, 2013·6 cites·19 claims
- 1480US8896344B1Heterogeneous programmable device and configuration software adapted thereforALTERA CORP·Filed 2013·Granted Nov 25, 2014·4 cites·22 claims
- 1579US10832787B2Methods for memory interface calibrationALTERA CORP·Filed 2019·Granted Nov 10, 2020·2 cites·11 claims
- 1679US7360190B1Method and apparatus for performing retiming on field programmable gate arraysALTERA CORP·Filed 2004·Granted Apr 15, 2008·25 cites·31 claims
- 1779US7257800B1Method and apparatus for performing logic replication in field programmable gate arraysALTERA CORP·Filed 2004·Granted Aug 14, 2007·28 cites·34 claims
- 1877US9030231B1Heterogeneous programmable device and configuration software adapted thereforALTERA CORP·Filed 2014·Granted May 12, 2015·3 cites·20 claims
- 1976US8201114B1Method and apparatus for performing look up table unpacking and repacking for resynthesisMANOHARARAJAH VALAVAN·Filed 2009·Granted Jun 12, 2012·7 cites·30 claims
- 2076US7620925B1Method and apparatus for performing post-placement routability optimizationALTERA CORP·Filed 2006·Granted Nov 17, 2009·7 cites·16 claims
- 2174US9245085B2Integrated circuit device configuration methods adapted to account for retimingALTERA CORP·Filed 2014·Granted Jan 26, 2016·2 cites·24 claims
- 2274US7290239B1Method and apparatus for performing post-placement functional decomposition for field programmable gate arraysALTERA CORP·Filed 2004·Granted Oct 30, 2007·18 cites·14 claims
- 2373US8904318B1Method and apparatus for performing optimization using don't care statesALTERA CORP·Filed 2014·Granted Dec 2, 2014·3 cites·25 claims
- 2472US8581624B2Integrated circuits with multi-stage logic regionsCASHMAN DAVID·Filed 2012·Granted Nov 12, 2013·4 cites·19 claims
- 2571US7509597B1Method and apparatus for performing post-placement functional decomposition on field programmable gate arrays using binary decision diagramsALTERA CORP·Filed 2005·Granted Mar 24, 2009·5 cites·19 claims
- 2671US7444613B1Systems and methods for mapping arbitrary logic functions into synchronous embedded memoriesALTERA CORP·Filed 2006·Granted Oct 28, 2008·4 cites·38 claims
- 2771US7412677B1Detecting reducible registersALTERA CORP·Filed 2006·Granted Aug 12, 2008·5 cites·30 claims
- 2870US2021082534A1Methods for memory interface calibrationALTERA CORP·Filed 2020·Application pending·0 cites
- 2968US10019234B2Methods and apparatus for sequencing multiply-accumulate operationsALTERA CORP·Filed 2015·Granted Jul 10, 2018·1 cites·20 claims
- 3068US7565387B1Systems and methods for configuring a programmable logic device to perform a computation using carry chainsALTERA CORP·Filed 2005·Granted Jul 21, 2009·7 cites·19 claims
- 3167US8578306B2Method and apparatus for performing asynchronous and synchronous reset removal during synthesisMANOHARARAJAH VALAVAN·Filed 2010·Granted Nov 5, 2013·2 cites·27 claims
- 3265US10452392B1Configuring programmable integrated circuit device resources as processorsALTERA CORP·Filed 2015·Granted Oct 22, 2019·1 cites·25 claims
- 3365US9360884B2Clocking for pipelined routingALTERA CORP·Filed 2013·Granted Jun 7, 2016·1 cites·24 claims
- 3464US7797666B1Systems and methods for mapping arbitrary logic functions into synchronous embedded memoriesALTERA CORP·Filed 2008·Granted Sep 14, 2010·2 cites·20 claims
- 3563US8645885B1Specification of multithreading in programmable device configurationALTERA CORP·Filed 2013·Granted Feb 4, 2014·1 cites·19 claims
- 3663US7594204B1Method and apparatus for performing layout-driven optimizations on field programmable gate arraysALTERA CORP·Filed 2003·Granted Sep 22, 2009·8 cites·17 claims
- 3761US8661381B1Method and apparatus for performing optimization using Don't Care statesMALHOTRA SHAWN·Filed 2008·Granted Feb 25, 2014·2 cites·36 claims
- 3860US10572224B2Methods and apparatus for sequencing multiply-accumulate operationsALTERA CORP·Filed 2018·Granted Feb 25, 2020·0 cites·20 claims
- 3959US9589090B1Method and apparatus for performing multiple stage physical synthesisALTERA CORP·Filed 2014·Granted Mar 7, 2017·0 cites·25 claims
- 4056US8839172B1Specification of latency in programmable device configurationALTERA CORP·Filed 2014·Granted Sep 16, 2014·0 cites·26 claims
- 4154US10332612B2Methods for memory interface calibrationALTERA CORP·Filed 2018·Granted Jun 25, 2019·0 cites·8 claims
- 4253US9911506B1Methods for memory interface calibrationALTERA CORP·Filed 2017·Granted Mar 6, 2018·0 cites·12 claims
- 4353US8713496B1Specification of latency in programmable device configurationALTERA COPORATION·Filed 2013·Granted Apr 29, 2014·0 cites·20 claims
- 4452US10037396B2Integrated circuit device configuration methods adapted to account for retimingALTERA CORP·Filed 2015·Granted Jul 31, 2018·0 cites·24 claims
- 4552US9401718B1Heterogeneous programmable device and configuration software adapted thereforALTERA CORP·Filed 2015·Granted Jul 26, 2016·0 cites·20 claims
- 4650US2016239043A1Clocking for pipelined routingALTERA CORP·Filed 2016·Application pending·0 cites
- 4748US9100011B1Pipelined direct drive routing fabricALTERA CORP·Filed 2015·Granted Aug 4, 2015·0 cites·15 claims
- 4845US9891904B1Method and apparatus for optimizing implementation of a soft processor executing a fixed program on a target deviceWONG JASON·Filed 2010·Granted Feb 13, 2018·0 cites·20 claims
- 4938US8847624B1Method and system for operating a circuitMANOHARARAJAH VALAVAN·Filed 2012·Granted Sep 30, 2014·0 cites·19 claims
- 5030US2012110400A1Method and Apparatus for Performing Memory Interface CalibrationMANOHARARAJAH VALAVAN·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →