Inventor

ZHANG QINTAO

US83 patents

⚠️ This page may combine multiple inventors who share the name “ZHANG QINTAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZHANG QINTAO

IBM

High density nanosheet diodes

Integrating standard-gate and extended-gate nanosheet transistors on the same substrate

Stacked nanosheet field effect transistor device with substrate isolation

Vertical transistor having uniform bottom spacers

Integrating thin and thick gate dielectric nanosheet transistors on same chip

Forming horizontal bipolar junction transistor compatible with nanosheets

Nanosheet transistors having different gate dielectric thicknesses on the same chip

iFinFET

Nanosheet capacitor

High density nanosheet diodes

Nanosheet transistors having different gate dielectric thicknesses on the same chip

Forming horizontal bipolar junction transistor compatible with nanosheets

One-time programmable vertical field-effect transistor

Vertical antifuse structures

Integrated device with P-I-N diodes and vertical field effect transistors

Integrated LDMOS and VFET transistors

FinFET formation with late fin reveal

Stacked nanosheet field effect transistor device with substrate isolation

Nanosheet transistors having different gate dielectric thicknesses on the same chip

IFinFET

Vertical field effect transistor including integrated antifuse

Forming gates with varying length using sidewall image transfer

Nanosheet capacitor

Vertical transistor having uniform bottom spacers

Inductor with ferromagnetic cores

Manufacturing method for inductor with ferromagnetic cores

Integrated LDMOS and VFET transistors

Forming gates with varying length using sidewall image transfer

APPLIED MATERIALS INC

Ion implantation to reduce nanosheet gate length variation

System and method for hi-precision ion implantation

Techniques and apparatus for anisotropic stress compensation in substrates using ion implantation

Selective implantation into STI of ETSOI device

Minority carrier lifetime reduction for SiC IGBT devices

Methods for forming N-type buried layer in a substrate by performing non-doping implant through oxide layer formed over the substrate

Backside wafer dopant activation

Method of forming stress memorization layer on backside of semiconductor substrate and semiconductor device thereof

DRAM transistor including horizonal body contact

Method of forming a 4F2 DRAM including buried bitline

Bottom contact formation for 4F2 vertical DRAM

Vertical FinFet formation using directional deposition

Etch rate modulation of FinFET through high-temperature ion implantation

Ion implantation to increase MOSFET threshold voltage

Technique for reducing gate induced drain leakage in DRAM cells

Ion implantation to form step-oxide trench MOSFET

Angled ion implant to reduce MOSFET trench sidewall roughness

Replacement metal gate formation of PMOS ultra-low voltage devices using a thermal implant

SAMSUNG ELECTRONICS CO LTD

Vertical field effect transistor including integrated antifuse

Vertical field effect transistor including integrated antifuse

BROADCOM CORP

Super junction LDMOS finFET devices

AVAGO TECHNOLOGIES GENERAL IP

One time programmable memory with a twin gate structure