Ion implantation to form step-oxide trench MOSFET

Abstract

Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming a gate spacer layer over the device structure, and removing the gate spacer layer from a top surface of the device structure and from a first section of each of the plurality of trenches, wherein a portion of the gate spacer layer remains along a second section of each of the plurality of trenches. The method may further include forming a gate oxide layer along the first section of each of the plurality of trenches and along the portion of the gate spacer layer.

What is claimed is: 
     
       1. A method, comprising:
 providing a device structure including a plurality of trenches; 
 forming a gate spacer layer over the device structure; 
 removing the gate spacer layer from a top surface of the device structure and selective to a first section of a sidewall of each of the plurality of trenches to expose the sidewall, wherein a portion of the gate spacer layer remains along a second section of the sidewall in a lower section of each of the plurality of trenches; 
 forming a gate oxide layer along the first section of the sidewall of each of the plurality of trenches and along the portion of the gate spacer layer; and 
 forming a gate material within the lower section of each of the plurality of trenches, wherein the gate spacer layer is removed prior to formation of the gate material. 
 
     
     
       2. The method of  claim 1 , wherein forming the gate material comprises forming the gate material over the gate oxide layer within each of the plurality of trenches. 
     
     
       3. The method of  claim 2 , wherein removing the gate spacer layer further comprises etching the device structure to remove the gate spacer layer from a bottom surface of each of the plurality of trenches. 
     
     
       4. The method of  claim 3 , further comprising performing an ion implantation to the device structure to form a treated layer along the bottom surface of each of the plurality of trenches and along the top surface of the device structure. 
     
     
       5. The method of  claim 4 , further comprising thermally oxidizing the device structure to form the gate oxide layer from the treated layer along the bottom surface of each of the plurality of trenches. 
     
     
       6. The method of  claim 2 , further comprising:
 forming a second gate oxide layer along the first section of each of the plurality of trenches; and 
 forming a second gate material over the second gate oxide layer. 
 
     
     
       7. The method of  claim 6 , wherein forming the second gate oxide layer comprises forming a gate isolation layer over the gate material, and wherein the second gate material is formed over the gate isolation layer. 
     
     
       8. The method of  claim 1 , wherein removing the gate spacer layer comprises performing a vertical ion etch to the gate spacer layer. 
     
     
       9. The method of  claim 1 , wherein removing the gate spacer layer from the first section of the sidewall of each of the plurality of trenches comprises performing an angled ion etch. 
     
     
       10. The method of  claim 9 , wherein the angled ion etch is prevented from impacting the first second section of the sidewall of each of the plurality of trenches. 
     
     
       11. A method of forming a MOSFET, comprising:
 providing a device structure including a plurality of trenches; 
 forming a gate spacer layer over the device structure including within the plurality of trenches; 
 etching the device structure to remove the gate spacer layer selective to a top surface of the device structure and selective to an upper section of a sidewall of each of the plurality of trenches to expose the sidewall, wherein a portion of the gate spacer layer remains along a lower section of each of the plurality of trenches; 
 forming a gate oxide layer along the upper section of the sidewall of each of the plurality of trenches and along the portion of the gate spacer layer; and 
 forming a gate material over the gate oxide layer, wherein the gate material is formed within the lower section of each of the plurality of trenches, and wherein the gate spacer layer is removed prior to formation of the gate material. 
 
     
     
       12. The method of  claim 11 , wherein etching the device structure further comprises removing the gate spacer layer from a bottom surface of each of the plurality of trenches. 
     
     
       13. The method of  claim 12 , further comprising:
 performing, after the device structure is etched, an ion implantation to the device structure to form a treated layer along the bottom surface of each of the plurality of trenches and along the top surface of the device structure; and 
 forming the gate oxide layer along the bottom surface of each of the plurality of trenches and along the top surface of the device stack by thermally oxidizing the treated layer. 
 
     
     
       14. The method of  claim 11 , further comprising:
 forming a second gate oxide layer along the upper section of each of the plurality of trenches; and 
 forming a second gate material over the second gate oxide layer. 
 
     
     
       15. The method of  claim 14 , wherein forming the second gate oxide layer further comprises forming a gate isolation layer over the gate material, and wherein the second gate material is formed directly atop the gate isolation layer. 
     
     
       16. The method of  claim 11 , wherein etching the device structure comprises:
 performing a vertical ion etch; and 
 performing an angled ion etch to the upper section of the sidewall of each of the plurality of trenches, wherein the angled ion etch is oriented at a non-zero angle of inclination relative to a perpendicular extending from the top surface of the device structure. 
 
     
     
       17. A method of forming a semiconductor device, comprising:
 forming a gate spacer layer within a plurality of trenches of a device structure; 
 removing the gate spacer layer selective to an upper section of a sidewall of each of the plurality of trenches to expose the sidewall, wherein a portion of the gate spacer layer remains along a lower section of the sidewall in a lower section of each of the plurality of trenches; 
 forming a gate oxide layer along the upper section of the sidewall of each of the plurality of trenches and along the portion of the gate spacer layer; and 
 forming a gate material over the gate oxide layer, wherein the gate material is formed within the lower section of each of the plurality of trenches, and wherein the gate spacer layer is removed prior to formation of the gate material. 
 
     
     
       18. The method of  claim 17 , further comprising removing the gate spacer layer from a top surface of the device structure, wherein the gate spacer layer is an oxide material. 
     
     
       19. The method of  claim 18 , further comprising:
 performing an ion implantation to the device structure to form a treated layer along a bottom surface of each of the plurality of trenches and along the top surface of the device structure; and 
 forming the gate oxide layer along the bottom surface of each of the plurality of trenches and along the top surface of the device stack by thermally oxidizing the treated layer. 
 
     
     
       20. The method of  claim 17 , further comprising:
 forming a gate isolation layer over the gate material; and 
 forming a second gate material within the plurality of trenches, over the gate isolation layer.