Inventor

GU SIPENG

US60 patents

⚠️ This page may combine multiple inventors who share the name “GU SIPENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GU SIPENG

GLOBALFOUNDRIES US INC

Gate structures

Memory device comprising a top via electrode and methods of making such a memory device

Top electrode for a memory device and methods of making such a memory device

Self-aligned contact

Transistors with separately-formed source and drain

Transistors with source/drain regions having sections of epitaxial semiconductor material

Gate capping layers of semiconductor devices

IC products formed on a substrate having localized regions of high resistivity and methods of making such IC products

LDMOS integrated circuit product

Transistors with separately-formed source and drain

Semiconductor structures in a wide gate pitch region of semiconductor devices

Memory device comprising a top via electrode and methods of making such a memory device

Three part source/drain region structure for transistor

Via structures for use in semiconductor devices

Transistors with a sectioned epitaxial semiconductor layer

Gate structures

Semiconductor devices having late-formed isolation structures

Transistor device having sidewall spacers contacting lower surfaces of an epitaxial semiconductor material

Memory device and methods of making such a memory device

Methods of forming a replacement gate structure for a transistor device

Transistors with a hybrid source or drain

Semiconductor devices with wide gate-to-gate spacing

Multi-level isolation structure

GLOBALFOUNDRIES INC

Interconnect formation process using wire trench etch prior to via etch, and related interconnect

Fin-type field effect transistors with single-diffusion breaks and method

Metal-insulator-metal capacitors with enlarged contact areas

Multiple Fin heights with dielectric isolation

Planar metrology pad adjacent a set of fins of a fin field effect transistor device

Gate cut first isolation formation with contact forming process mask protection

Method to form high performance fin profile for 12LP and above

Dimension-controlled via formation processing

Diffusion break structures in semiconductor devices

Vertical-transport field-effect transistors with an etched-through source/drain cavity

Dimension-controlled via formation processing

Planar metrology pad adjacent a set of fins of a fin field effect transistor device

Integrated circuit structure to reduce soft-fail incidence and method of forming same

Metal resistors with a non-planar configuration

Method of forming smooth sidewall structures using spacer materials

APPLIED MATERIALS INC

Ion implantation to reduce nanosheet gate length variation

DRAM transistor including horizonal body contact

Method of forming a 4F2 DRAM including buried bitline

Bottom contact formation for 4F2 vertical DRAM

Vertical FinFet formation using directional deposition

Techniques for selective tungsten contact formation on semiconductor device elements

Technique for reducing gate induced drain leakage in DRAM cells

Ion implantation to form step-oxide trench MOSFET

Ion implantation to reduce nanosheet gate length variation

Localized stressor formation by ion implantation

Isolation method to enable continuous channel layer

Handling for high resistivity substrates