Ion implantation to reduce nanosheet gate length variation

Abstract

Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

What is claimed is: 
     
       1. A method, comprising:
 implanting a gate structure to modify first and second areas of a gate material layer; and 
 etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath a hardmask. 
 
     
     
       2. The method of  claim 1 , further comprising:
 forming the gate structure over a nanosheet stack, the gate structure including the hardmask atop the gate material layer; and 
 removing a portion of the hardmask to expose the first and second areas of the gate material layer. 
 
     
     
       3. The method of  claim 2 , further comprising:
 forming a spacer along the treated layer; and 
 removing a portion of the nanosheet stack to form an active gate, wherein a sidewall of the spacer is co-planar with a sidewall of the active gate. 
 
     
     
       4. The method of  claim 2 , further comprising forming the treated layer beneath the hardmask. 
     
     
       5. The method of  claim 2 , further comprising depositing a series of alternating layers of silicon and silicon germanium to form the nanosheet stack. 
     
     
       6. The method of  claim 5 , further comprising forming an etch stop layer atop the series of alternating layers of silicon and silicon germanium, wherein the gate structure is formed over the etch stop layer. 
     
     
       7. The method of  claim 1 , further comprising modifying the first and second areas of the gate material layer by amorphizing the first and second areas or by doping the first and second areas with ions of the implant. 
     
     
       8. The method of  claim 1 , wherein implanting the gate structure comprises performing a vertical ion implant to the gate structure, wherein the gate material layer is amorphous silicon. 
     
     
       9. A method of reducing gate length variation, comprising:
 forming a dummy gate structure over a nanosheet stack; 
 implanting the dummy gate structure to modify first and second areas of a silicon layer; and 
 etching the first and second areas of the silicon layer to form a treated layer along a sidewall of a third area of the silicon layer, wherein the third area is beneath a hardmask, and wherein the hardmask is formed over the silicon layer. 
 
     
     
       10. The method of  claim 9 , further comprising forming a spacer along the treated layer, wherein the spacer extends to a top surface of the dummy gate structure. 
     
     
       11. The method of  claim 10 , further comprising removing a portion of the nanosheet stack to form an active gate, wherein a sidewall of the spacer is co-planar with a sidewall of the active gate. 
     
     
       12. The method of  claim 9 , further comprising forming the treated layer beneath the hardmask. 
     
     
       13. The method of  claim 9 , further comprising:
 depositing a series of alternating layers of silicon and silicon germanium to form the nanosheet stack; and 
 forming an etch stop layer atop the series of alternating layers of silicon and silicon germanium, wherein the silicon layer is formed over the etch stop layer. 
 
     
     
       14. The method of  claim 9 , further comprising removing a portion of the hardmask to expose a first area and a second area of the silicon layer. 
     
     
       15. The method of  claim 14 , further comprising modifying the first and second areas of the silicon layer by amorphizing the first and second areas or by doping the first and second areas with n-type phosphorous ions, arsenic ions, or antimony ions. 
     
     
       16. A method of reducing lateral etch rate variation, comprising:
 forming a gate structure over a nanosheet stack, the gate structure including a hardmask atop a gate material layer; 
 removing a portion of the hardmask to expose a first area and a second area of the gate material layer, wherein the hardmask remains over a third area of the gate material layer; 
 implanting the gate structure to modify the first and second areas of the gate material layer; and 
 etching the first and second areas of the gate material layer to form a treated layer along a sidewall of the third area of the gate material layer. 
 
     
     
       17. The method of  claim 16 , further comprising:
 forming a spacer along the treated layer; and 
 etching the nanosheet stack to form an active gate beneath the third area of the gate material layer, wherein a sidewall of the spacer is co-planar with a sidewall of the active gate, and wherein the treated layer is formed beneath the hardmask. 
 
     
     
       18. The method of  claim 16 , further comprising:
 depositing a series of alternating layers of silicon and silicon germanium to form the nanosheet stack; and 
 forming an etch stop layer atop the series of alternating layers of silicon and silicon germanium, wherein the gate structure is formed over the etch stop layer. 
 
     
     
       19. The method of  claim 16 , further comprising modifying the first and second areas of the gate material layer by amorphizing the first and second areas or by doping the first and second areas with an ion implant. 
     
     
       20. The method of  claim 16 , further comprising performing a vertical ion implant to the gate structure to modify the first and second areas of the gate material layer, wherein the gate material layer is amorphous silicon.