Inventor · disambiguated record
Jesus Mennen Belonio, Jr.
Also filed as: BELONIO JESUS MENNEN · BELONIO JR JESUS MENNEN
17 granted patents·4 pending applications·63 citations·filing 2006–2022
91Inventor score
Files withDIALOG SEMICONDUCTOR UK LTD16DIALOG SEMICONDUCTOR BV2INFINEON TECHNOLOGIES AG2DOBRITZ STEPHAN1
Top patents by PatentIndex Score
21 records- 0190US7732242B2Composite board with semiconductor chips and plastic housing composition and methodINFINEON TECHNOLOGIES AG·Filed 2007·Granted Jun 8, 2010·22 cites·6 claims
- 0288US10083926B1Stress relief solutions on WLCSP large/bulk copper plane designDIALOG SEMICONDUCTOR UK LTD·Filed 2017·Granted Sep 25, 2018·11 cites·12 claims
- 0386US10629507B1System in package (SIP)DIALOG SEMICONDUCTOR UK LTD·Filed 2018·Granted Apr 21, 2020·5 cites·8 claims
- 0485US10636742B2Very thin embedded trace substrate-system in package (SIP)DIALOG SEMICONDUCTOR UK LTD·Filed 2017·Granted Apr 28, 2020·4 cites·16 claims
- 0584US11239185B2Embedded resistor-capacitor film for fan out wafer level packagingDIALOG SEMICONDUCTOR UK LTD·Filed 2017·Granted Feb 1, 2022·3 cites·11 claims
- 0679US7667333B2Stack of semiconductor chipsINFINEON TECHNOLOGIES AG·Filed 2006·Granted Feb 23, 2010·12 cites·15 claims
- 0778US11094669B2Wafer level molded PPGA (pad post grid array) for low cost packageDIALOG SEMICONDUCTOR BV·Filed 2019·Granted Aug 17, 2021·2 cites·15 claims
- 0876US11621218B1Single side modular 3D stack up SiP with mold cavityDIALOG SEMICONDUCTOR UK LTD·Filed 2021·Granted Apr 4, 2023·1 cites·14 claims
- 0973US11075167B2Pillared cavity down MIS-SIPDIALOG SEMICONDUCTOR UK LTD·Filed 2019·Granted Jul 27, 2021·2 cites·3 claims
- 1066US12100674B2Embedded resistor-capacitor film for fan out wafer level packagingDIALOG SEMICONDUCTOR UK LTD·Filed 2022·Granted Sep 24, 2024·0 cites·15 claims
- 1165US11114359B2Wafer level chip scale package structureDIALOG SEMICONDUCTOR UK LTD·Filed 2018·Granted Sep 7, 2021·1 cites·14 claims
- 1258US11532489B2Pillared cavity down MIS-SiPDIALOG SEMICONDUCTOR UK LTD·Filed 2021·Granted Dec 20, 2022·0 cites·15 claims
- 1358US11309255B2Very thin embedded trace substrate-system in package (SIP)DIALOG SEMICONDUCTOR UK LTD·Filed 2020·Granted Apr 19, 2022·0 cites·14 claims
- 1454US12205750B23D MIS-FO hybrid for embedded inductor package structureDIALOG SEMICONDUCTOR UK LTD·Filed 2021·Granted Jan 21, 2025·0 cites·19 claims
- 1549US2019181115A1Wafer Level Molded PPGA (Pad Post Grid Array) for Low Cost PackageDIALOG SEMICONDUCTOR UK LTD·Filed 2017·Application pending·0 cites
- 1646US11158551B2Modular WLCSP die daisy chain design for multiple die sizesDIALOG SEMICONDUCTOR UK LTD·Filed 2020·Granted Oct 26, 2021·0 cites·12 claims
- 1743US11251132B1Integrated type MIS substrate for thin double side SIP packageDIALOG SEMICONDUCTOR UK LTD·Filed 2019·Granted Feb 15, 2022·0 cites·15 claims
- 1841US10727174B2Integrated circuit package and a method for forming a wafer level chip scale package (WLCSP) with through mold via (TMV)DIALOG SEMICONDUCTOR UK LTD·Filed 2018·Granted Jul 28, 2020·0 cites·25 claims
- 1939US2007279877A1Circuit board arrangementDOBRITZ STEPHAN·Filed 2006·Application pending·0 cites
- 2038US2019267342A1Wafer Level UGA (UBM Grid Array) & PGA (Pad Grid Array) for Low Cost PackageDIALOG SEMICONDUCTOR BV·Filed 2018·Application pending·0 cites
- 2132US2018025965A1WFCQFN (Very-Very Thin Flip Chip Quad Flat No Lead) with Embedded Component on Leadframe and Method ThereforDIALOG SEMICONDUCTOR UK LTD·Filed 2016·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →