Inventor

WONG ROBERT C

US76 patents

⚠️ This page may combine multiple inventors who share the name “WONG ROBERT C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WONG ROBERT C

IBM

SRAM cell with dynamic split ground and split wordline

Method and apparatus for writing operation in SRAM cells employing PFETS pass gates

CMOS SRAM cell with PFET passgate devices

Process for making and programming a flash memory array

Process for making and programming a flash memory array

SRAM design to facilitate single fin cut in double sidewall image transfer process

SRAM cell with dynamic split ground and split wordline

Integration scheme for multiple metal gate work function structures

SRAM active write assist method for improved operational margins

SRAM having active write assist for improved operational margins

Real-time adaptive SRAM array for high SEU immunity

SRAM with improved noise sensitivity

Secure and dense SRAM cells in EDRAM technology

Process for making and programming a flash memory array

One-transistor static random access memory with integrated vertical PNPN device

SRAM voltage control for improved operational margins

Method and apparatus for identifying SRAM cells having weak pull-up PFETs

Variable data compensation for vias or contacts

SRAM cell with dynamic split ground and split wordline

SRAM cell with dynamic split ground and split wordline

SRAM cell with dynamic split ground and split wordline

SRAM cell with dynamic split ground and split wordline

Partially gated FINFET with gate dielectric on only one sidewall

SRAM cell design to improve stability

Design structure for SRAM active write assist for improved operational margins

Structure and method for improved SRAM interconnect

SRAM cell design to improve stability

Discriminative SOI with oxide holes underneath DC source/drain

Ultra high-speed DDP-SRAM cache

Apparatus and method for detecting defective NVRAM cells

High density SRAM cell with hybrid devices

Process for making and programming a flash memory array

Secure and static 4T SRAM cells in EDRAM technology

Bipolar memory cell with isolated PNP load

One stage word line decoder/driver with speed-up Darlington drive and adjustable pull down

Adjustable clock chopper/expander circuit

Semiconductor memory device and array

Integrated circuit design layout optimizer based on process variation and failure mechanism

Cross-coupling of gate conductor line and active region in semiconductor devices

Dense SRAM cells with selective SOI

Content addressable memory with PFET passgate SRAM cells

Memory cell with active device for saturation capacitance discharge prior to writing

GLOBALFOUNDRIES INC

Semiconductor structures with stacked non-planar field effect transistors and methods of forming the structures

Stable and reliable FinFET SRAM with improved beta ratio

TESSERA LLC

Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic

Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic

HEYMANN OMER

Boost cell supply write assist

SARDESAI VIRAJ Y

Cross-coupling of gate conductor line and active region in semiconductor devices

BUTT SHAHID A

FinFET device

ADEIA SEMICONDUCTOR SOLUTIONS LLC

Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic