Adjustable clock chopper/expander circuit

Abstract

A clock chopper/expander circuit 10 includes a reset dominant latch circuit 20 which is set by a CLOCK IN signal 12 and reset by a delayed CLOCK IN signal labelled DELAY 26, provided by an asymmetrical delay circuit 22 which delays the CLOCK IN signal TD seconds. The delay circuit 22 utilizes an adjustable bias current source 64 to bias a half memory cell 50, which charges up a node 62 according to the write time of the cell 50. A sensing circuit triggers a DELAY transition when node 62 crosses a voltage predetermined by the bias provided to a second half memory cell 52 which is also controlled by the bias current source 64. A multiplexer 24 provides disablement of the clock chopping/expanding function and an OR gate 14 facilitates easy measurement of the actual delay introduced by circuit 22.

What is claimed is: 
     
       1. A clock chopper/expander circuit for either chopping or expanding a clock input signal comprising: first cell means responsive to the clock input signal for charging up a first voltage of a first node for each low to high transition of the clock input signal, and discharging said first voltage for each high to low transition of the clock input signal, for providing a delayed clock signal indicative of said first voltage; and   reset dominant latch means having a set input responsive to the clock input signal and a reset input responsive to said delayed clock signal, for providing a clock output signal indicative of a set or reset status of said reset dominant latch means, wherein said reset dominant latch means is set if the clock input signal is logic high and said delayed clock signal is logic low and said reset dominant latch means is reset if said delayed clock signal is logic high.   
     
     
       2. The clock chopper/expander circuit according to claim 1, further comprising first bias current means for providing a bias current to said first cell means, wherein a time required for said first cell means to charge up said first voltage is dependent upon said bias current. 
     
     
       3. The clock chopper/expander circuit according to claim 2, further comprising: comparator means for comparing said first voltage with a predetermined reference voltage for providing said delayed clock signal, wherein said comparator means changes said delayed clock signal in direct relation to said first voltage being either greater or lesser than said predetermined reference voltage; and   second cell means responsive to said bias current for charging up a second voltage at a second node in proportion to said bias current, wherein said predetermined reference voltage is indicative of said second voltage.   
     
     
       4. The clock chopper/expander circuit according to claim 1, further comprising comparator means for comparing said first voltage with a predetermined reference voltage for providing said delayed clock signal, wherein said comparator means changes said delay clock signal in direct relation to said first voltage being either greater or lesser than said predetermined reference voltage. 
     
     
       5. The clock chopper/expander circuit according to claim 1, further comprising level shifter means responsive to said delayed clock signal for providing a shifted delayed clock signal proportional to said delayed clock signal. 
     
     
       6. The clock chopper/expander circuit according to claim 5, wherein said shifted delayed clock signal has a voltage swing on the order of 0.3 volts higher than the voltage swing of the clock input signal. 
     
     
       7. The clock chopper/expander circuit according to claim 1, wherein said first cell means is additionally responsive to said clock output signal, wherein said first cell charges up said first voltage when either the clock input signal or said clock output signal are logic high, and discharges the voltage at said first node when both the clock input signal and said clock output signal are logic low. 
     
     
       8. The clock chopper/expander circuit according to claim 1, further comprising: OR gate means responsive to the clock input signal and a test signal for performing an OR function thereto and for providing an OR signal indicative of the OR function result to said set input of said reset dominant latch means, wherein said reset dominant latch means is responsive to said OR signal and said delayed clock signal.   
     
     
       9. The clock chopper/expander circuit according to claim 1, further comprising: multiplexer means responsive to an enable signal for multiplexing the clock input signal and said delayed clock signal, wherein said multiplexer means provides an inverted clock input signal to said reset input if said enable signal is logic high, and provides said delayed clock signal to said reset input if said enable signal is logic low.   
     
     
       10. A clock chopper/expander circuit for either chopping or expanding a clock input signal comprising: delay circuit means responsive to the clock input signal for providing a delayed clock signal wherein a low to high transition of said delayed clock signal occurs TD seconds after each low to high transition of the clock input signal, said delay circuit having: a) a first transistor connected between a first supply voltage and a first node, the control gate of said first transistor being responsive to the clock input signal;   b) first cell circuit means connected in parallel with said first transistor for charging up a second voltage at a second node when the clock input signal is high and discharging said first voltage when the clock input signal is low, said first cell circuit having a first cell for charging up said second node, and   c) a second transistor connected in series with said first cell, having a control gate connected to a first reference voltage, a collector connected to said second node, and an emitter connected to said first node;   d) current source means connected to said first node for controlling a first current from said first node;   e) comparator means for comparing a first voltage at said first node with a predetermined reference voltage and for providing said delayed clock signal, wherein said comparator means changes said delayed clock signal in direct relation to said first voltage being either greater or lesser than said predetermined reference voltage; and     reset dominant latch means having a set input responsive to the clock input signal and a reset input responsive to said delayed clock signal, for providing a clock output signal indicative of a set or reset status of said reset dominant latch means, wherein said reset dominant latch means is set if the clock input signal is logic high and said delayed clock signal signal is logic low and said reset dominant latch means is reset if said delayed clock signal is logic high.   
     
     
       11. The clock chopper/expander circuit according to claim 10, wherein said first cell comprises: a third and a fourth npn transistor having their respective emitters, collectors, and bases connected to said second node;   a fifth pnp transistor having a collector connected to said first supply voltage, and an emitter and a base connected to said second node.   
     
     
       12. The clock chopper/expander circuit according to claim 10, wherein said current source means comprises: a sixth npn transistor having a collector connected to said first node, an emitter connected to said second supply voltage, and a base connected to a bias current means for providing an adjustable bias current thereto,   wherein said sixth npn transistor is connected in a current switch configuration with said first and second transistor means.   
     
     
       13. The clock chopper/expander circuit according to claim 10, wherein said current source means comprises: a seventh npn transistor for controlling said first current, and having a collector connected to said first node, an emitter connected to said second supply voltage, and a base connected to a third node;   an eighth npn transistor for controlling a second current through said seventh transistor, and having an emitter connected to said second supply voltage, and a collector and a base connected to said third node;   a first resistor connected between said first supply voltage and said third node;   a first and a second Schottky diode connected oppositely and in parallel between said third node and a fourth node for filtering noise below the Schottky voltage of said Schottky diodes from said second node;   a second resistor connected between said fourth node and a fifth node for limiting a third current at said third node;   filter means for filtering electrostatic voltages and noise from said fourth node and having a third resistor connected between said first supply voltage and said fourth node, a third diode having a cathode connected to said first supply voltage and an anode connected to said fourth node, a fourth resistor connected between said second supply voltage and said fourth node, and a fourth diode having a cathode connected to said fourth node and an anode connected to said second supply voltage; and   external, adjustable bias current supply means for providing bias current to said fourth node.   
     
     
       14. The clock chopper/expander circuit according to claim 10, further comprising: ninth transistor connected between said first supply voltage and said first node, having a control gate responsive to said clock output signal, wherein the current from said first node is shared by said first, second, and ninth transistors.   
     
     
       15. The clock chopper/expander circuit according to claim 10, further comprising a voltage bias means responsive to said current source means for providing said second reference voltage in proportion to the amplitude of the current from said first node. 
     
     
       16. The clock chopper/expander circuit according to claim 10, further comprising a second cell circuit means responsive to said current source means for charging up said predetermined reference voltage at said second node in proportion to said first current. 
     
     
       17. The clock chopper/expander circuit according to claim 10, further comprising a second cell circuit means responsive to said current control means for providing said reference voltage in proportion to said first current, said second cell circuit means comprising: a tenth and an eleventh npn transistor having their respective emitters, collectors, and bases connected to a fifth node;   a twelfth pnp transistor having a collector connected to said first supply voltage, and an emitter and a base connected to said fifth node.   a sixth resistor connected between said fifth node and a sixth node;   a seventh resistor connected between said sixth node and said first supply voltage;   a thirteenth npn transistor having a collector connected to said first supply, an emitter connected to a seventh node, and a base connected to said sixth node; and   an eighth resistor connected between said seventh node and said second supply voltage,   wherein said reference voltage is the voltage at said seventh node.   
     
     
       18. The clock chopper/expander circuit according to claim 10, further comprising: level shifter means responsive to said delayed clock signal for shifting said delayed clock signal and providing a shifted delayed clock signal to said reset input of said reset dominant latch means.   
     
     
       19. The clock chopper/expander circuit according to claim 18, wherein said shifted delayed clock signal has a voltage swing shifted on the order of 0.3 volts higher than the voltage swing of the clock input signal. 
     
     
       20. A clock chopper/expander circuit for either chopping or expanding a clock input signal comprising: delay circuit means responsive to the clock input signal for providing a repetitive delayed clock signal wherein a low to high transition said delayed clock signal occurs TD seconds after each low to high transition of the clock input signal, said delay circuit having: a) a first transistor, a second transistor, a third transistor and a fourth transistor connected in a current switch configuration, said fourth transistor controlling a first shared current through said first, second and third transistors, wherein the control gate of said first transistor is connected to the clock input signal, the control gate of said second transistor is connected to a clock output signal, and the control gate of said third transistor is connected to a first reference voltage, and wherein said third transistor is turned on only when both said first and said second transistors are turned off;   b) a current bias source connected to the control gate of said fourth transistor for controlling a first current through said fourth transistor;   c) a first half memory cell connected in series with said third transistor, for charging up a first voltage at a first node when said third transistor is turned off, and discharging said first voltage when said third transistor is turned on;   d) comparator means for comparing said first voltage with a predetermined reference voltage for providing said delayed clock signal, wherein said comparator means changes said delayed clock signal in direct relation to the voltage at said first node being either greater or lesser than said predetermined reference voltage;     level shifter means responsive to said delayed clock signal for providing a reset signal proportional to said delayed clock signal, said reset signal having a voltage swing shifted on the order of 0.3 volts higher than the voltage swing of the clock input signal; and   reset dominant latch means having a set input responsive to the clock input signal and a reset input responsive to said reset signal, for providing a clock output signal indicative of a set or reset status of said reset dominant latch means, wherein said reset dominant latch means is set if the clock input signal is logic high and said reset signal is logic low and said reset dominant latch means is reset if said reset signal is logic high.   
     
     
       21. The clock chopper/expander circuit according to claim 20, wherein said comparator means comprises: a fifth, a sixth, and a seventh transistor connected in a current switch configuration, said seventh transistor controlling a second shared current through said fifth and sixth transistors, said fifth transistor having a control gate responsive to said first voltage, said sixth transistor having a control gate connected to a second reference voltage, and said seventh transistor having a control gate connected to a third reference voltage;   a first pull up resistor connected to the collector of said fifth transistor.   
     
     
       22. The clock chopper/expander circuit according to claim 20, further comprising a second cell responsive to said current source means for charging up said predetermined reference voltage at said second node in proportion to a second current from said first node. 
     
     
       23. The clock chopper/expander circuit according to claim 20, further comprising: OR gate means responsive to the clock input signal and a test signal for performing an OR function thereto and for providing an OR signal indicative of the OR function result to said set input of said reset dominant latch means, wherein said reset dominant latch means is responsive to said OR signal and said reset signal.   
     
     
       24. The clock chopper/expander circuit according to claim 20, further comprising: multiplexer means responsive to an enable signal for multiplexing the clock input signal and said reset signal, wherein said multiplexer means provides an inverted clock input signal to said reset input if said enable signal is logic high, and provides said reset signal to said reset input if said enable signal is logic low.