Inventor

BANDOH TADAAKI

JP41 patents

Patents

41 patents

US5784630AJul 21, 1998

Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory

HITACHI LTD127 citations99

US5133064AJul 21, 1992

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

HITACHI LTD182 citations99

US4454578AJun 12, 1984

Data processing unit with pipelined operands

HITACHI LTD158 citations99

US5968160AOct 19, 1999

Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory

HITACHI LTD75 citations96

US5561775AOct 1, 1996

Parallel processing apparatus and method capable of processing plural instructions in parallel or successively

HITACHI LTD47 citations96

US5542083AJul 30, 1996

Information processor and information processing system utilizing clock signal

HITACHI LTD37 citations96

US5404472AApr 4, 1995

Parallel processing apparatus and method capable of switching parallel and successive processing modes

HITACHI LTD43 citations96

US5388249AFeb 7, 1995

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

HITACHI LTD41 citations96

US5287465AFeb 15, 1994

Parallel processing apparatus and method capable of switching parallel and successive processing modes

HITACHI LTD42 citations96

US5247649ASep 21, 1993

Multi-processor system having a multi-port cache memory

HITACHI LTD76 citations96

US4839846AJun 13, 1989

Apparatus for performing floating point arithmetic operations and rounding the result thereof

HITACHI LTD91 citations96

US4811269AMar 7, 1989

Bit slice multiplication circuit

HITACHI LTD95 citations96

US4523274AJun 11, 1985

Data processing system with processors having different processing speeds sharing a common bus

HITACHI LTD60 citations96

US4481573ANov 6, 1984

Shared virtual address translation unit for a multiprocessor system

HITACHI LTD134 citations96

US4523272AJun 11, 1985

Bus selection control in a data transmission apparatus for a multiprocessor system

HITACHI LTD88 citations95

US4365311ADec 21, 1982

Control of instruction pipeline in data processing system

HITACHI LTD30 citations93

US5974560AOct 26, 1999

Information processor and information processing system utilizing clock signal

HITACHI LTD20 citations92

US5506982AApr 9, 1996

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

HITACHI LTD21 citations92

US5003458AMar 26, 1991

Suspended instruction restart processing system based on a checkpoint microprogram address

HITACHI LTD31 citations92

US4807113AFeb 21, 1989

Microprogrammed control data processing apparatus in which operand source and/or operand destination is determined independent of microprogram control

HITACHI LTD24 citations92

US4783731ANov 8, 1988

Multicomputer system having dual common memories

HITACHI LTD38 citations92

US4644490AFeb 17, 1987

Floating point data adder

HITACHI LTD30 citations92

US4530050AJul 16, 1985

Central processing unit for executing instructions of variable length having end information for operand specifiers

HITACHI LTD55 citations92

US4520441AMay 28, 1985

Data processing system

HITACHI LTD38 citations92

US5146569ASep 8, 1992

System for storing restart address of microprogram, determining the validity, and using valid restart address to resume execution upon removal of suspension

HITACHI LTD29 citations91

US5297239AMar 22, 1994

Compile type knowledge processing tool, a high-speed inference method therefor and a system using the tool

HITACHI LTD20 citations84

US6675311B2Jan 6, 2004

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

HITACHI LTD11 citations82

US5640547AJun 17, 1997

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

HITACHI LTD13 citations82

US4296468AOct 20, 1981

Address conversion unit for data processing system

HITACHI LTD22 citations82

US4095268AJun 13, 1978

System for stopping and restarting the operation of a data processor

HITACHI LTD29 citations82

US5274829ADec 28, 1993

Information processing apparatus having micro instructions stored both in on-chip ROM and off-chip memory

HITACHI LTD17 citations74

US4975839ADec 4, 1990

Instruction decode method and arrangement suitable for a decoder of microprocessors

HITACHI LTD11 citations74

US4853890AAug 1, 1989

Operation control apparatus for a processor having a plurality of arithmetic devices

HITACHI LTD11 citations73

US4896258AJan 23, 1990

Data processor provided with instructions which refer to both tagged and tagless data

HITACHI LTD16 citations73

US3986169AOct 12, 1976

Device protection method and apparatus

HITACHI LTD18 citations73

US3947818AMar 30, 1976

Bus-coupler

HITACHI LTD9 citations73

US7111187B2Sep 19, 2006

Information processor and information processing system utilizing interface for synchronizing clock signal

HITACHI LTD1 citations63

US5422980AJun 6, 1995

Inference processing method and apparatus

HITACHI LTD4 citations63

BANDOH TADAAKI

Patents

Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Data processing unit with pipelined operands

Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory

Parallel processing apparatus and method capable of processing plural instructions in parallel or successively

Information processor and information processing system utilizing clock signal

Parallel processing apparatus and method capable of switching parallel and successive processing modes

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Parallel processing apparatus and method capable of switching parallel and successive processing modes

Multi-processor system having a multi-port cache memory

Apparatus for performing floating point arithmetic operations and rounding the result thereof

Bit slice multiplication circuit

Data processing system with processors having different processing speeds sharing a common bus

Shared virtual address translation unit for a multiprocessor system

Bus selection control in a data transmission apparatus for a multiprocessor system

Control of instruction pipeline in data processing system

Information processor and information processing system utilizing clock signal

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Suspended instruction restart processing system based on a checkpoint microprogram address

Microprogrammed control data processing apparatus in which operand source and/or operand destination is determined independent of microprogram control

Multicomputer system having dual common memories

Floating point data adder

Central processing unit for executing instructions of variable length having end information for operand specifiers

Data processing system

System for storing restart address of microprogram, determining the validity, and using valid restart address to resume execution upon removal of suspension

Compile type knowledge processing tool, a high-speed inference method therefor and a system using the tool

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Address conversion unit for data processing system

System for stopping and restarting the operation of a data processor

Information processing apparatus having micro instructions stored both in on-chip ROM and off-chip memory

Instruction decode method and arrangement suitable for a decoder of microprocessors

Vector processor

Multi-computer system having dual common memory

Logical cache memory for multi-processor system

Operation control apparatus for a processor having a plurality of arithmetic devices

Data processor provided with instructions which refer to both tagged and tagless data

Device protection method and apparatus

Bus-coupler

Information processor and information processing system utilizing interface for synchronizing clock signal

Inference processing method and apparatus