Inventor

ZHOU BAOSUO

US37 patents

⚠️ This page may combine multiple inventors who share the name “ZHOU BAOSUO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZHOU BAOSUO

MICRON TECHNOLOGY INC

Simplified pitch doubling process flow

Methods to reduce the critical dimension of semiconductor devices

Protective coating for planarization

Methods for integrated circuit fabrication with protective coating for planarization

Method for forming high density patterns

Simplified pitch doubling process flow

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Simplified pitch doubling process flow

Methods for integrated circuit fabrication with protective coating for planarization

Method of forming a plurality of spaced features

Trim process for critical dimension control for integrated circuits

Trim process for critical dimension control for integrated circuits

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Simplified pitch doubling process flow

Method for forming high density patterns

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Method for forming and planarizing adjacent regions of an integrated circuit

Methods of patterning a material

ZHOU BAOSUO

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Methods to reduce the critical dimension of semiconductor devices and related semiconductor devices

Methods to reduce the critical dimension of semiconductor devices and related semiconductor devices

Method for forming high density patterns

Methods of forming patterns on substrates

LAM RES CORP

Cobalt etch back

Cobalt etch back

Method to etch copper barrier film

Method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber

LODESTAR LICENSING GROUP LLC

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

SIPANI VISHAL

Methods of patterning materials

Methods of forming openings

GOOD FARRELL

Method of forming a plurality of spaced features

ABATCHEV MIRZAFER

Methods for integrated circuit fabrication with protective coating for planarization

NIROOMAND ARDAVAN

Simplified pitch doubling process flow

Intel NDTM US LLC

Block-to-block isolation and deep contact using pillars in a memory array