Inventor
FUNG RYAN
CA76 patents
⚠️ This page may combine multiple inventors who share the name “FUNG RYAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
31 patentsUS9569574B1Feb 14, 2017
Method and apparatus for performing fast incremental physical design optimization
ALTERA CORP35 citations93
US7712067B1May 4, 2010
Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints
ALTERA CORP18 citations93
US7290232B1Oct 30, 2007
Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability
ALTERA CORP20 citations93
US7257795B1Aug 14, 2007
Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints
ALTERA CORP14 citations93
US8677298B1Mar 18, 2014
Programmable device configuration methods adapted to account for retiming
ALTERA CORP18 citations92
US7853911B1Dec 14, 2010
Method and apparatus for performing path-level skew optimization and analysis for a logic design
ALTERA CORP15 citations92
US7676768B1Mar 9, 2010
Automatic asynchronous signal pipelining
ALTERA CORP13 citations92
US7207020B1Apr 17, 2007
Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool
ALTERA CORP21 citations92
US6871328B1Mar 22, 2005
Method for mapping logic design memory into physical memory device of a programmable logic device
ALTERA CORP39 citations92
US9558849B1Jan 31, 2017
Methods for memory interface calibration
ALTERA CORP9 citations84
US9275178B1Mar 1, 2016
Method and apparatus for considering paths influenced by different power supply domains in timing analysis
ALTERA CORP14 citations84
US8863059B1Oct 14, 2014
Integrated circuit device configuration methods adapted to account for retiming
ALTERA CORP7 citations84
US8046729B1Oct 25, 2011
Method and apparatus for composing and decomposing low-skew networks
ALTERA CORP7 citations84
US7977975B1Jul 12, 2011
Apparatus for using metastability-hardened storage circuits in logic devices and associated methods
ALTERA CORP8 citations84
US7788614B1Aug 31, 2010
Method and apparatus for performing analytic placement techniques on logic devices with restrictive areas
ALTERA CORP12 citations84
US7737751B1Jun 15, 2010
Periphery clock distribution network for a programmable logic device
ALTERA CORP16 citations84
US7694256B1Apr 6, 2010
Method and apparatus for performing analytic placement techniques on logic devices with restrictive areas
ALTERA CORP9 citations84
US7370291B2May 6, 2008
Method for mapping logic design memory into physical memory devices of a programmable logic device
ALTERA CORP11 citations84
US7308664B1Dec 11, 2007
Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing
ALTERA CORP14 citations84
US7254789B1Aug 7, 2007
Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability
ALTERA CORP10 citations84
US7911240B1Mar 22, 2011
Clock switch-over circuits and methods
ALTERA CORP14 citations83
US7138844B2Nov 21, 2006
Variable delay circuitry
ALTERA CORP13 citations83
US8015382B1Sep 6, 2011
Method and apparatus for strobe-based source-synchronous capture using a first-in-first-out unit
ALTERA CORP5 citations74
US7629825B1Dec 8, 2009
Efficient delay elements
ALTERA CORP6 citations74
US10832787B2Nov 10, 2020
Methods for memory interface calibration
ALTERA CORP2 citations73
US11093672B2Aug 17, 2021
Method and apparatus for performing fast incremental physical design optimization
ALTERA CORP2 citations71
US10635772B1Apr 28, 2020
Method and apparatus for performing fast incremental physical design optimization
ALTERA CORP1 citations71
US9245085B2Jan 26, 2016
Integrated circuit device configuration methods adapted to account for retiming
ALTERA CORP2 citations63
US9183336B1Nov 10, 2015
Automatic asynchronous signal pipelining
ALTERA CORP1 citations63
US9166570B2Oct 20, 2015
Apparatus for using metastability-hardened storage circuits in logic devices and associated methods
ALTERA CORP3 citations63
US8856713B1Oct 7, 2014
Method and apparatus for performing efficient incremental compilation
ALTERA CORP1 citations63
FUNG RYAN
11 patentsUS8588014B1Nov 19, 2013
Methods for memory interface calibration
FUNG RYAN36 citations98
US8775701B1Jul 8, 2014
Method and apparatus for source-synchronous capture using a first-in-first-out unit
FUNG RYAN25 citations93
US9697309B1Jul 4, 2017
Metastability-hardened synchronization circuit
FUNG RYAN10 citations84
US8949763B1Feb 3, 2015
Apparatus and methods for optimization of integrated circuits
FUNG RYAN10 citations84
US8732639B1May 20, 2014
Method and apparatus for protecting, optimizing, and reporting synchronizers
FUNG RYAN9 citations84
US8572530B1Oct 29, 2013
Method and apparatus for performing path-level skew optimization and analysis for a logic design
FUNG RYAN5 citations84
US8261218B1Sep 4, 2012
Systems and methods for determining beneficial clock-path connection delays
FUNG RYAN13 citations84
US8255860B1Aug 28, 2012
Exploiting independent portions of logic designs for timing optimization
FUNG RYAN13 citations84
US8904331B1Dec 2, 2014
Method and apparatus for performing time domain jitter modeling
FUNG RYAN5 citations73
US8930597B1Jan 6, 2015
Method and apparatus for supporting low-latency external memory interfaces for integrated circuits
FUNG RYAN6 citations68
US8930175B1Jan 6, 2015
Method and apparatus for performing timing analysis that accounts for rise/fall skew
FUNG RYAN3 citations63
PADALIA KETAN
3 patentsUS8281274B1Oct 2, 2012
Method and apparatus for performing efficient incremental compilation
PADALIA KETAN23 citations92
US8539418B1Sep 17, 2013
Method and apparatus for performing efficient incremental compilation
PADALIA KETAN10 citations83
US9594859B1Mar 14, 2017
Apparatus and associated methods for parallelizing clustering and placement
PADALIA KETAN8 citations82
IMS HEALTH INCORPORATED
2 patentsMANOHARARAJAH VALAVAN
1 patentFENDER JOSHUA DAVID
1 patentGOUTERMAN VADIM
1 patentShowing the top 50 of 76 patents by PatentIndex Score.