Inventor
DUDHA CHAITHANYA
US13 patents
Patents
13 patentsUS10678983B1Jun 9, 2020
Local retiming optimization for circuit designs
XILINX INC2 citations72
US10430539B1Oct 1, 2019
Method and apparatus for enhancing performance by moving or adding a pipelined register stage in a cascaded chain
XILINX INC5 citations72
US10990736B1Apr 27, 2021
Implementing a circuit design with re-convergence
XILINX INC2 citations71
US10387600B2Aug 20, 2019
Dynamic power reduction in circuit designs and circuits
XILINX INC2 citations71
US10366001B1Jul 30, 2019
Partitioning memory blocks for reducing dynamic power consumption
XILINX INC4 citations70
US11100267B1Aug 24, 2021
Multi dimensional memory compression using bytewide write enable
XILINX INC2 citations67
US10606979B1Mar 31, 2020
Verifying equivalence of design latency
XILINX INC1 citations61
US10289786B1May 14, 2019
Circuit design transformation for automatic latency reduction
XILINX INC1 citations60
US11188697B1Nov 30, 2021
On-chip memory access pattern detection for power and resource reduction
XILINX INC0 citations59
US10726175B1Jul 28, 2020
Systems for optimization of read-only memory (ROM)
XILINX INC0 citations50
US11429769B1Aug 30, 2022
Implementing a hardware description language memory using heterogeneous memory primitives
XILINX INC0 citations47
US11842168B2Dec 12, 2023
Circuit architecture for determining threshold ranges and values of a dataset
XILINX INC0 citations38
US10642951B1May 5, 2020
Register pull-out for sequential circuit blocks in circuit designs
XILINX INC0 citations37