Systems for optimization of read-only memory (ROM)

Abstract

A memory optimization method includes identifying, within a circuit design, a memory having an arithmetic operator at an output side and/or an input side of the memory. The memory may include a read-only memory (ROM). In some examples, an input of the arithmetic operator includes a constant value. In some embodiments, the memory optimization method further includes absorbing a function of the arithmetic operator into the memory. By way of example, the absorbing the function includes modifying contents of the memory based on the function of the arithmetic operator to provide an updated memory and removing the arithmetic operator from the circuit design.

What is claimed is: 
     
       1. A memory optimization method, comprising:
 identifying, within a circuit design, a memory having an arithmetic operator at an output side of the memory, wherein a first input of the arithmetic operator includes a constant value; and 
 absorbing a function of the arithmetic operator into the memory, wherein the absorbing the function includes:
 modifying contents of the memory based on the function of the arithmetic operator to provide an updated memory; and 
 removing the arithmetic operator from the circuit design. 
 
 
     
     
       2. The memory optimization method of  claim 1 ,
 wherein the identifying further includes identifying that the memory drives a second input of the arithmetic operator. 
 
     
     
       3. The memory optimization method of  claim 1 ,
 wherein the identifying further includes identifying that the memory drives one or more registers and identifying that the one or more registers drive a second input of the arithmetic operator. 
 
     
     
       4. The memory optimization method of  claim 3 , further comprising:
 based on the identifying, performing a forward retiming of the one or more registers to modify the circuit design so that the memory drives the second input of the arithmetic operator; and 
 after the performing the forward retiming, absorbing the function of the arithmetic operator into the memory. 
 
     
     
       5. The memory optimization method of  claim 1 , further comprising:
 determining whether an output of the arithmetic operator is registered or whether an address of the memory is registered. 
 
     
     
       6. The memory optimization method of  claim 5 , further comprising:
 based on the determining, evaluating a memory mapping cost function, wherein the memory mapping cost function is determined based on a width of the updated memory, a depth of the updated memory, and a sparseness of the updated memory. 
 
     
     
       7. The memory optimization method of  claim 6 , further comprising:
 based on the evaluating the memory mapping cost function, mapping the updated memory to a dedicated random-access memory block (BRAM), wherein the mapping the updated memory to the BRAM includes absorbing the function of the arithmetic operator into the memory. 
 
     
     
       8. A memory output optimization method, comprising:
 identifying a circuit design including a data pipeline having a first stage that includes a read-only memory (ROM) and a second stage that includes an arithmetic operator, wherein the arithmetic operator has a first input that includes a constant value, and wherein the second stage is disposed at an output side of the first stage; 
 modifying each word of a memory array of the ROM based on a function of the arithmetic operator to provide an updated ROM; and 
 removing the arithmetic operator from the circuit design. 
 
     
     
       9. The memory output optimization method of  claim 8 ,
 wherein the identifying further includes identifying the data pipeline having a third stage disposed between the first stage and the second stage, wherein the third stage includes a register, and wherein the register drives a second input of the arithmetic operator. 
 
     
     
       10. The memory output optimization method of  claim 9 , further comprising:
 based on the identifying, performing a forward retiming of the register to modify the circuit design so that the ROM drives the second input of the arithmetic operator; and 
 after the performing the forward retiming, modifying each word of the memory array of the ROM and removing the arithmetic operator from the circuit design. 
 
     
     
       11. The memory output optimization method of  claim 10 ,
 wherein the forward retiming further modifies the circuit design so that the arithmetic operator drives the register; and 
 wherein the removing the arithmetic operator from the circuit design further includes modifying the circuit design so that the updated ROM drives the register. 
 
     
     
       12. The memory output optimization method of  claim 10 , further comprising:
 after the performing the forward retiming and before the modifying each word of the memory array of the ROM, evaluating a memory mapping cost function. 
 
     
     
       13. The memory output optimization method of  claim 12 ,
 wherein the memory mapping cost function is determined based on a width of the updated ROM, a depth of the updated ROM, and a sparseness of the updated ROM. 
 
     
     
       14. The memory output optimization method of  claim 12 , further comprising:
 based on the evaluating the memory mapping cost function, mapping the updated ROM to a dedicated random-access memory block (BRAM). 
 
     
     
       15. A memory input optimization method, comprising:
 identifying a data pipeline within a circuit design, wherein the data pipeline includes an arithmetic operator at an input side of a read-only memory (ROM), and wherein a first input of the arithmetic operator includes a constant value; and 
 absorbing a function of the arithmetic operator into the ROM, wherein the absorbing the function includes:
 modifying contents of the ROM based on the function of the arithmetic operator to provide an updated ROM; and 
 removing the arithmetic operator from the data pipeline. 
 
 
     
     
       16. The memory input optimization method of  claim 15 ,
 wherein the identifying further includes identifying that the arithmetic operator drives an address input of the ROM. 
 
     
     
       17. The memory input optimization method of  claim 15 ,
 wherein the identifying further includes identifying that the arithmetic operator drives one or more registers and identifying that the one or more registers drive an address input of the ROM. 
 
     
     
       18. The memory input optimization method of  claim 17 , further comprising:
 based on the identifying, performing a backward retiming of the one or more registers to modify the circuit design so that the arithmetic operator drives the address input of the ROM; and 
 after the performing the backward retiming, absorbing the function of the arithmetic operator into the ROM. 
 
     
     
       19. The memory input optimization method of  claim 15 ,
 wherein the modifying the contents of the ROM further includes shifting an address location by the constant value to a shifted address location; 
 wherein the modifying the contents of the ROM further includes retrieving data from the shifted address location; and 
 storing the retrieved data into the address location. 
 
     
     
       20. The memory input optimization method of  claim 15 , further comprising:
 before the absorbing the function of the arithmetic operator into the ROM, evaluating a memory mapping cost function, wherein the memory mapping cost function is determined based on a width of the updated ROM, a depth of the updated ROM, and a sparseness of the updated ROM.