Inventor · disambiguated record
Chaithanya Dudha
Also filed as: DUDHA CHAITHANYA
13 granted patents·5 pending applications·19 citations·filing 2016–2023
86Inventor score
Files withXILINX INC18
Top patents by PatentIndex Score
18 records- 0185US10430539B1Method and apparatus for enhancing performance by moving or adding a pipelined register stage in a cascaded chainXILINX INC·Filed 2016·Granted Oct 1, 2019·5 cites·20 claims
- 0283US10990736B1Implementing a circuit design with re-convergenceXILINX INC·Filed 2020·Granted Apr 27, 2021·2 cites·20 claims
- 0382US10366001B1Partitioning memory blocks for reducing dynamic power consumptionXILINX INC·Filed 2017·Granted Jul 30, 2019·4 cites·15 claims
- 0480US11100267B1Multi dimensional memory compression using bytewide write enableXILINX INC·Filed 2020·Granted Aug 24, 2021·2 cites·20 claims
- 0576US10678983B1Local retiming optimization for circuit designsXILINX INC·Filed 2018·Granted Jun 9, 2020·2 cites·20 claims
- 0672US10387600B2Dynamic power reduction in circuit designs and circuitsXILINX INC·Filed 2016·Granted Aug 20, 2019·2 cites·20 claims
- 0768US10606979B1Verifying equivalence of design latencyXILINX INC·Filed 2018·Granted Mar 31, 2020·1 cites·20 claims
- 0868US10289786B1Circuit design transformation for automatic latency reductionXILINX INC·Filed 2017·Granted May 14, 2019·1 cites·20 claims
- 0954US11188697B1On-chip memory access pattern detection for power and resource reductionXILINX INC·Filed 2021·Granted Nov 30, 2021·0 cites·20 claims
- 1053US2023297824A1Programmable non-linear activation engine for neural network accelerationXILINX INC·Filed 2022·Application pending·0 cites
- 1152US2025005249A1Smart predictor circuitry insertion based on structural analysis and switching activityXILINX INC·Filed 2023·Application pending·0 cites
- 1251US10726175B1Systems for optimization of read-only memory (ROM)XILINX INC·Filed 2019·Granted Jul 28, 2020·0 cites·20 claims
- 1351US2025148179A1Area optimized memory implementation using dedicated memory primitivesXILINX INC·Filed 2023·Application pending·0 cites
- 1449US2024256749A1Retiming sequential elements having initital statesXILINX INC·Filed 2023·Application pending·0 cites
- 1546US11429769B1Implementing a hardware description language memory using heterogeneous memory primitivesXILINX INC·Filed 2020·Granted Aug 30, 2022·0 cites·20 claims
- 1646US10642951B1Register pull-out for sequential circuit blocks in circuit designsXILINX INC·Filed 2018·Granted May 5, 2020·0 cites·20 claims
- 1743US11842168B2Circuit architecture for determining threshold ranges and values of a datasetXILINX INC·Filed 2021·Granted Dec 12, 2023·0 cites·20 claims
- 1842US2022261523A1Behavioral-level timing and area optimiationXILINX INC·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →