Inventor · disambiguated record
Ashish Sirasao
Also filed as: SIRASAO ASHISH
40 granted patents·2 pending applications·372 citations·filing 2013–2024
98Inventor score
Top patents by PatentIndex Score
42 records- 0197US10515135B1Data format suitable for fast massively parallel general matrix multiplication in a programmable ICXILINX INC·Filed 2017·Granted Dec 24, 2019·25 cites·20 claims
- 0297US10354733B1Software-defined memory bandwidth reduction by hierarchical stream buffering for general matrix multiplication in a programmable ICXILINX INC·Filed 2017·Granted Jul 16, 2019·40 cites·20 claims
- 0396US10572225B1Circuit arrangements and methods for performing multiply-and-accumulate operationsXILINX INC·Filed 2018·Granted Feb 25, 2020·26 cites·20 claims
- 0495US10572409B1Sparse matrix processing circuitryXILINX INC·Filed 2018·Granted Feb 25, 2020·54 cites·20 claims
- 0595US10460416B1Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuitXILINX INC·Filed 2017·Granted Oct 29, 2019·19 cites·17 claims
- 0694US11204747B1Re-targetable interface for data exchange between heterogeneous systems and accelerator abstraction into software instructionsXILINX INC·Filed 2017·Granted Dec 21, 2021·19 cites·20 claims
- 0793US10331836B1Loop optimization for implementing circuit designs in hardwareXILINX INC·Filed 2017·Granted Jun 25, 2019·20 cites·20 claims
- 0892US10411709B1Circuit arrangements and methods for dividing a three-dimensional input feature mapXILINX INC·Filed 2018·Granted Sep 10, 2019·13 cites·20 claims
- 0991US10747502B2Multiply and accumulate circuitXILINX INC·Filed 2018·Granted Aug 18, 2020·13 cites·18 claims
- 1090US11449347B1Time-multiplexed implementation of hardware accelerated functions in a programmable integrated circuitXILINX INC·Filed 2019·Granted Sep 20, 2022·7 cites·18 claims
- 1190US10943039B1Software-driven design optimization for fixed-point multiply-accumulate circuitryXILINX INC·Filed 2017·Granted Mar 9, 2021·11 cites·20 claims
- 1290US10678509B1Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulatorsXILINX INC·Filed 2018·Granted Jun 9, 2020·11 cites·20 claims
- 1389US9875330B2Folding duplicate instances of modules in a circuit designXILINX INC·Filed 2015·Granted Jan 23, 2018·7 cites·20 claims
- 1488US11222256B2Neural network processing system having multiple processors and a neural network acceleratorXILINX INC·Filed 2017·Granted Jan 11, 2022·8 cites·15 claims
- 1587US11106968B1Circuit arrangements and methods for traversing input feature mapsXILINX INC·Filed 2018·Granted Aug 31, 2021·7 cites·20 claims
- 1687US11036827B1Software-defined buffer/transposer for general matrix multiplication in a programmable ICXILINX INC·Filed 2017·Granted Jun 15, 2021·7 cites·20 claims
- 1787US10936311B1Sparse matrix processing circuitryXILINX INC·Filed 2019·Granted Mar 2, 2021·8 cites·20 claims
- 1886US8769450B1Synthesis flow for formal verificationXILINX INC·Filed 2013·Granted Jul 1, 2014·9 cites·20 claims
- 1985US12086572B1Software defined neural network layer pipeliningXILINX INC·Filed 2017·Granted Sep 10, 2024·6 cites·17 claims
- 2085US10990826B1Object detection in videoXILINX INC·Filed 2019·Granted Apr 27, 2021·9 cites·15 claims
- 2185US10430539B1Method and apparatus for enhancing performance by moving or adding a pipelined register stage in a cascaded chainXILINX INC·Filed 2016·Granted Oct 1, 2019·5 cites·20 claims
- 2285US10303833B1Parallelizing timing-based operations for circuit designsXILINX INC·Filed 2017·Granted May 28, 2019·6 cites·20 claims
- 2383US11568218B2Neural network processing system having host controlled kernel accleratorsXILINX INC·Filed 2017·Granted Jan 31, 2023·5 cites·20 claims
- 2483US10990736B1Implementing a circuit design with re-convergenceXILINX INC·Filed 2020·Granted Apr 27, 2021·2 cites·20 claims
- 2581US10984500B1Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuitXILINX INC·Filed 2019·Granted Apr 20, 2021·3 cites·20 claims
- 2681US8667436B1Object identification in an electronic circuit designXILINX INC·Filed 2013·Granted Mar 4, 2014·6 cites·20 claims
- 2780US11429848B2Host-directed multi-layer neural network processing via per-layer work requestsXILINX INC·Filed 2017·Granted Aug 30, 2022·4 cites·14 claims
- 2878US10824434B1Dynamically structured single instruction, multiple data (SIMD) instructionsXILINX INC·Filed 2018·Granted Nov 3, 2020·2 cites·20 claims
- 2976US11620490B2Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructionsXILINX INC·Filed 2017·Granted Apr 4, 2023·3 cites·14 claims
- 3076US11386644B2Image preprocessing for generalized image processingXILINX INC·Filed 2017·Granted Jul 12, 2022·2 cites·17 claims
- 3176US10678983B1Local retiming optimization for circuit designsXILINX INC·Filed 2018·Granted Jun 9, 2020·2 cites·20 claims
- 3276US9268891B1Compact and efficient circuit implementation of dynamic ranges in hardware description languagesXILINX INC·Filed 2014·Granted Feb 23, 2016·3 cites·20 claims
- 3373US9460253B1Selecting predefined circuit implementations in a circuit design systemXILINX INC·Filed 2014·Granted Oct 4, 2016·3 cites·19 claims
- 3473US9235498B1Circuits for and methods of enabling the modification of an input data streamXILINX INC·Filed 2013·Granted Jan 12, 2016·5 cites·20 claims
- 3568US10289786B1Circuit design transformation for automatic latency reductionXILINX INC·Filed 2017·Granted May 14, 2019·1 cites·20 claims
- 3661US8938700B1Data-driven pattern matching in synthesis of circuit designsXILINX INC·Filed 2013·Granted Jan 20, 2015·1 cites·20 claims
- 3758US2025190221A1Systems and methods for parallelization of embedding operationsADVANCED MICRO DEVICES INC·Filed 2024·Application pending·0 cites
- 3854US11188697B1On-chip memory access pattern detection for power and resource reductionXILINX INC·Filed 2021·Granted Nov 30, 2021·0 cites·20 claims
- 3951US10726175B1Systems for optimization of read-only memory (ROM)XILINX INC·Filed 2019·Granted Jul 28, 2020·0 cites·20 claims
- 4047US11694066B2Machine learning runtime library for neural network accelerationXILINX INC·Filed 2017·Granted Jul 4, 2023·0 cites·20 claims
- 4147US2023153583A1Compilation of neural networks into subgraphs for processing by multiple compute circuitsXILINX INC·Filed 2021·Application pending·0 cites
- 4244US12061990B2Static block scheduling in massively parallel software defined hardware systemsXILINX INC·Filed 2017·Granted Aug 13, 2024·0 cites·17 claims
Join the waitlist — get patent alerts
Get an alert when Ashish Sirasao files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →