Inventor

RAMASWAMY RAHUL

US46 patents

Patents

46 patents

US11094782B1Aug 17, 2021

Gate-all-around integrated circuit structures having depopulated channel structures

INTEL CORP8 citations83

US11387328B2Jul 12, 2022

III-N tunnel device architectures and high frequency mixers employing a III-N tunnel device

INTEL CORP6 citations75

US12369358B2Jul 22, 2025

Co-integrated high performance nanoribbon transistors with high voltage thick gate finFET devices

INTEL CORP2 citations73

US11588037B2Feb 21, 2023

Planar transistors with wrap-around gates and wrap-around source and drain contacts

INTEL CORP2 citations73

US11437483B2Sep 6, 2022

Gate-all-around integrated circuit structures having dual nanoribbon channel structures

INTEL CORP2 citations72

US10756210B2Aug 25, 2020

Nanoribbon thick gate devices with differential ribbon spacing and width for SOC applications

INTEL CORP1 citations63

US12148757B2Nov 19, 2024

Integration of Si-based transistors with non-Si technologies by semiconductor regrowth over an insulator material

INTEL CORP0 citations62

US12027613B2Jul 2, 2024

III-N transistor arrangements for reducing nonlinearity of off-state capacitance

INTEL CORP0 citations62

US11881511B2Jan 23, 2024

Superlattice FINFET with tunable drive current capability

INTEL CORP1 citations62

US11848362B2Dec 19, 2023

III-N transistors with contacts of modified widths

INTEL CORP0 citations62

US11757027B2Sep 12, 2023

E-D mode 2DEG FET with gate spacer to locally tune VT and improve breakdown

INTEL CORP0 citations62

US11715790B2Aug 1, 2023

Charge-induced threshold voltage tuning in III-N transistors

INTEL CORP0 citations62

US11658217B2May 23, 2023

Transistors with ion- or fixed charge-based field plate structures

INTEL CORP0 citations62

US11527532B2Dec 13, 2022

Enhancement-depletion cascode arrangements for enhancement mode III-N transistors

INTEL CORP0 citations62

US11450617B2Sep 20, 2022

Transmission line structures for III-N devices

INTEL CORP0 citations62

US11075286B2Jul 27, 2021

Hybrid finfet structure with bulk source/drain regions

INTEL CORP0 citations62

US10964690B2Mar 30, 2021

Resistor between gates in self-aligned gate edge architecture

INTEL CORP1 citations62

US10930729B2Feb 23, 2021

Fin-based thin film resistor

INTEL CORP0 citations62

US12453145B2Oct 21, 2025

Single gated 3D nanowire inverter for high density thick gate SoC applications

INTEL CORP0 citations61

US12349411B2Jul 1, 2025

Gate-all-around integrated circuit structures having dual nanoribbon channel structures

INTEL CORP0 citations61

US11862703B2Jan 2, 2024

Gate-all-around integrated circuit structures having dual nanoribbon channel structures

INTEL CORP0 citations61

US11791380B2Oct 17, 2023

Single gated 3D nanowire inverter for high density thick gate SOC applications

INTEL CORP0 citations61

US11581404B2Feb 14, 2023

Gate-all-around integrated circuit structures having depopulated channel structures

INTEL CORP0 citations61

US11581313B2Feb 14, 2023

Integration of III-N transistors and non-III-N transistors by semiconductor regrowth

INTEL CORP0 citations61

US11610971B2Mar 21, 2023

Cap layer on a polarization layer to preserve channel sheet resistance

INTEL CORP0 citations60

US10811751B2Oct 20, 2020

Monolithic splitter using re-entrant poly silicon waveguides

INTEL CORP1 citations60

US11652143B2May 16, 2023

III-N transistors integrated with thin-film transistors having graded dopant concentrations and/or composite gate dielectrics

INTEL CORP0 citations59

US11688788B2Jun 27, 2023

Transistor gate structure with hybrid stacks of dielectric material

INTEL CORP0 citations57

US12089411B2Sep 10, 2024

Self-aligned front-end charge trap flash memory cell and capacitor design for integrated high-density scaled devices

INTEL CORP0 citations56

US12108595B2Oct 1, 2024

Integrated fuse in self-aligned gate endcap for FinFET architectures and methods of fabrication

INTEL CORP0 citations52

US11670709B2Jun 6, 2023

III-N transistors with local stressors for threshold voltage control

INTEL CORP0 citations52

US11587924B2Feb 21, 2023

Integration of passive components in III-N devices

INTEL CORP0 citations52

US9741721B2Aug 22, 2017

Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM)

INTEL CORP1 citations52

US12568682B2Mar 3, 2026

Nanoribbon thick gate device with hybrid dielectric tuning for high breakdown and VT modulation

INTEL CORP0 citations51

US12040395B2Jul 16, 2024

High voltage extended-drain MOS (EDMOS) nanowire transistors

INTEL CORP0 citations51

US11502191B2Nov 15, 2022

Transistors with backside field plate structures

INTEL CORP0 citations51

US10854757B2Dec 1, 2020

FINFET based junctionless wrap around structure

INTEL CORP0 citations51

US10164115B2Dec 25, 2018

Non-linear fin-based devices

INTEL CORP0 citations51

US11996403B2May 28, 2024

ESD diode solution for nanoribbon architectures

INTEL CORP0 citations50

US11121040B2Sep 14, 2021

Multi voltage threshold transistors through process and design-induced multiple work functions

INTEL CORP0 citations50

US10761264B2Sep 1, 2020

Transmission lines using bending fins from local stress

INTEL CORP0 citations50

US10763209B2Sep 1, 2020

MOS antifuse with void-accelerated breakdown

INTEL CORP0 citations50

US11626513B2Apr 11, 2023

Antenna gate field plate on 2DEG planar FET

INTEL CORP0 citations49

RAMASWAMY RAHUL

Patents

Gate-all-around integrated circuit structures having depopulated channel structures

III-N tunnel device architectures and high frequency mixers employing a III-N tunnel device

Co-integrated high performance nanoribbon transistors with high voltage thick gate finFET devices

Planar transistors with wrap-around gates and wrap-around source and drain contacts

Gate-all-around integrated circuit structures having dual nanoribbon channel structures

Depletion mode gate in ultrathin FINFET based architecture

Multi-gate transistor with variably sized fin

Transistor gate metal with laterally graduated work function

Nanoribbon thick gate devices with differential ribbon spacing and width for SOC applications

Integration of Si-based transistors with non-Si technologies by semiconductor regrowth over an insulator material

III-N transistor arrangements for reducing nonlinearity of off-state capacitance

Superlattice FINFET with tunable drive current capability

III-N transistors with contacts of modified widths

E-D mode 2DEG FET with gate spacer to locally tune VT and improve breakdown

Charge-induced threshold voltage tuning in III-N transistors

Transistors with ion- or fixed charge-based field plate structures

Enhancement-depletion cascode arrangements for enhancement mode III-N transistors

Transmission line structures for III-N devices

Hybrid finfet structure with bulk source/drain regions

Resistor between gates in self-aligned gate edge architecture

Fin-based thin film resistor

Single gated 3D nanowire inverter for high density thick gate SoC applications

Gate-all-around integrated circuit structures having dual nanoribbon channel structures

Gate-all-around integrated circuit structures having dual nanoribbon channel structures

Single gated 3D nanowire inverter for high density thick gate SOC applications

Gate-all-around integrated circuit structures having depopulated channel structures

Integration of III-N transistors and non-III-N transistors by semiconductor regrowth

Cap layer on a polarization layer to preserve channel sheet resistance

Monolithic splitter using re-entrant poly silicon waveguides

III-N transistors integrated with thin-film transistors having graded dopant concentrations and/or composite gate dielectrics

Transistor gate structure with hybrid stacks of dielectric material

Self-aligned front-end charge trap flash memory cell and capacitor design for integrated high-density scaled devices

Integrated fuse in self-aligned gate endcap for FinFET architectures and methods of fabrication

III-N transistors with local stressors for threshold voltage control

Integration of passive components in III-N devices

Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM)

Nanoribbon thick gate device with hybrid dielectric tuning for high breakdown and VT modulation

High voltage extended-drain MOS (EDMOS) nanowire transistors

Transistors with backside field plate structures

FINFET based junctionless wrap around structure

Non-linear fin-based devices

ESD diode solution for nanoribbon architectures

Multi voltage threshold transistors through process and design-induced multiple work functions

Transmission lines using bending fins from local stress

MOS antifuse with void-accelerated breakdown

Antenna gate field plate on 2DEG planar FET