Inventor

ROBISON ROBERT

US58 patents

⚠️ This page may combine multiple inventors who share the name “ROBISON ROBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROBISON ROBERT

IBM

Barrier-less prefilled via formation

Top via with damascene line and via

Topological qubit device

Conductive lines with subtractive cuts

Well-controlled edge-to-edge spacing between adjacent interconnects

Top via stack

Top via interconnect having a line with a reduced bottom dimension

Top via with next level line selective growth

Top via with hybrid metallization

Spacer-assisted lithographic double patterning

Single-mask alternating line deposition

Top via interconnect having a line with a reduced bottom dimension

Interconnects having spacers for improved top via critical dimension and overlay tolerance

Top via with next level line selective growth

Top via cut fill process for line extension reduction

Conductive lines with subtractive cuts

Stepped top via for via resistance reduction

Barrier-less prefilled via formation

Top via stack

Single-mask alternating line deposition

Barrier removal for conductor in top via integration scheme

Subtractive line with damascene second line type

Interconnects having spacers for improved top via critical dimension and overlay tolerance

Top vias with selectively retained etch stops

Top via on subtractively etched conductive line

Stepped top via for via resistance reduction

Etch stop layer removal for capacitance reduction in damascene top via integration

Top via with damascene line and via

Top vias with subtractive line formation

Band gap modulated optical sensor

Back-end-of-line resistive semiconductor structures

Band gap modulated optical sensor

Field effect transistor and method of fabricating same

Wraparound contact with reduced distance to channel

Looped long channel field-effect transistor

Self-aligned C-shaped vertical field effect transistor

Fully aligned top vias

Source and drain contact cut last process to enable wrap-around-contact

High aspect ratio vias for integrated circuits

Fully aligned top vias

Self-aligned isolation for nanosheet transistor

Source and drain contact cut last process to enable wrap-around-contact

Spacer-confined epitaxial growth

Magnetoresistive random-access memory device including magnetic tunnel junctions

Composite material phase change memory cell

Conformal dielectric cap for subtractive vias

Stressed material within gate cut region

ABOU-KHALIL MICHEL J

Structures, methods and applications for electrical pulse anneal processes

INT BUSINESS MACHINES CORPORATION

Top via on subtractively etched conductive line

NAYFEH HASAN M

Structure and method for manufacturing asymmetric devices