Inventor
DE SILVA EKMINI ANUJA
US89 patents
Patents
50 patentsUS10304744B1May 28, 2019
Inverse tone direct print EUV lithography enabled by selective material deposition
IBM23 citations94
US10879107B2Dec 29, 2020
Method of forming barrier free contact for metal interconnects
IBM14 citations84
US10347486B1Jul 9, 2019
Patterning material film stack with metal-containing top coat for enhanced sensitivity in extreme ultraviolet (EUV) lithography
IBM5 citations83
US10276452B1Apr 30, 2019
Low undercut N-P work function metal patterning in nanosheet replacement metal gate process
IBM13 citations83
US11923246B2Mar 5, 2024
Via CD controllable top via structure
IBM4 citations75
US11923311B2Mar 5, 2024
Forming self-aligned multi-metal interconnects
IBM2 citations73
US11810828B2Nov 7, 2023
Transistor boundary protection using reversible crosslinking reflow
IBM2 citations73
US11621326B2Apr 4, 2023
Vertical field effect transistor with crosslink fin arrangement
IBM2 citations73
US11355442B2Jun 7, 2022
Forming self-aligned multi-metal interconnects
IBM2 citations73
US11251182B2Feb 15, 2022
Staggered stacked vertical crystalline semiconducting channels
IBM2 citations73
US10790372B2Sep 29, 2020
Direct gate metal cut using selective deposition to protect the gate end line from metal shorts
IBM5 citations73
US10622482B2Apr 14, 2020
Gate cut using selective deposition to prevent oxide loss
IBM4 citations73
US10347540B1Jul 9, 2019
Gate cut using selective deposition to prevent oxide loss
IBM3 citations73
US10170582B1Jan 1, 2019
Uniform bottom spacer for vertical field effect transistor
IBM6 citations73
US11307496B2Apr 19, 2022
Metal brush layer for EUV patterning
IBM2 citations72
US11037786B2Jun 15, 2021
Patterning material film stack with metal-containing top coat for enhanced sensitivity in extreme ultraviolet (EUV) lithography
IBM2 citations72
US10629495B2Apr 21, 2020
Low undercut N-P work function metal patterning in nanosheet replacement metal gate process
IBM2 citations72
US10374034B1Aug 6, 2019
Undercut control in isotropic wet etch processes
IBM5 citations72
US11239077B2Feb 1, 2022
Litho-etch-litho-etch with self-aligned blocks
IBM2 citations71
US10395925B2Aug 27, 2019
Patterning material film stack comprising hard mask layer having high metal content interface to resist layer
IBM4 citations71
US10545409B1Jan 28, 2020
Dynamic adjustment of post exposure bake during lithography utilizing real-time feedback for wafer exposure delay
IBM3 citations70
US12363913B2Jul 15, 2025
Fabrication of embedded memory devices utilizing a self assembled monolayer
IBM0 citations63
US12310100B2May 20, 2025
Dielectric reflow for boundary control
IBM0 citations63
US12002856B2Jun 4, 2024
Vertical field effect transistor with crosslink fin arrangement
IBM0 citations63
US11916143B2Feb 27, 2024
Vertical transport field-effect transistor with gate patterning
IBM0 citations63
US11744083B2Aug 29, 2023
Fabrication of embedded memory devices utilizing a self assembled monolayer
IBM1 citations63
US11521894B2Dec 6, 2022
Partial wrap around top contact
IBM0 citations63
US11515431B2Nov 29, 2022
Enabling residue free gap fill between nanosheets
IBM0 citations63
US11508823B2Nov 22, 2022
Low capacitance low RC wrap-around-contact
IBM1 citations63
US11043628B2Jun 22, 2021
Multi-layer bottom electrode for embedded memory devices
IBM0 citations63
US10957552B2Mar 23, 2021
Extreme ultraviolet lithography patterning with directional deposition
IBM0 citations63
US10658521B2May 19, 2020
Enabling residue free gap fill between nanosheets
IBM1 citations63
US12183630B2Dec 31, 2024
Additive interconnect formation
IBM0 citations62
US12125790B2Oct 22, 2024
Airgap isolation for back-end-of-the-line semiconductor interconnect structure with top via
IBM0 citations62
US12033856B2Jul 9, 2024
Litho-litho-etch (LLE) multi color resist
IBM0 citations62
US12020949B2Jun 25, 2024
Subtractive patterning of interconnect structures
IBM0 citations62
US11990342B2May 21, 2024
Metal cut patterning and etching to minimize interlayer dielectric layer loss
IBM0 citations62
US11856878B2Dec 26, 2023
High-density resistive random-access memory array with self-aligned bottom electrode contact
IBM0 citations62
US11830807B2Nov 28, 2023
Placing top vias at line ends by selective growth of via mask from line cut dielectric
IBM0 citations62
US11778929B2Oct 3, 2023
Selective encapsulation for metal electrodes of embedded memory devices
IBM1 citations62
US11756961B2Sep 12, 2023
Staggered stacked vertical crystalline semiconducting channels
IBM0 citations62
US11751492B2Sep 5, 2023
Embedded memory pillar
IBM0 citations62
US11699592B2Jul 11, 2023
Inverse tone pillar printing method using organic planarizing layer pillars
IBM0 citations62
US11682558B2Jun 20, 2023
Fabrication of back-end-of-line interconnects
IBM0 citations62
US11500293B2Nov 15, 2022
Patterning material film stack with hard mask layer configured to support selective deposition on patterned resist layer
IBM0 citations62
US11302573B2Apr 12, 2022
Semiconductor structure with fully aligned vias
IBM1 citations62
US11300881B2Apr 12, 2022
Line break repairing layer for extreme ultraviolet patterning stacks
IBM0 citations62
US11189561B2Nov 30, 2021
Placing top vias at line ends by selective growth of via mask from line cut dielectric
IBM0 citations62
US11177130B2Nov 16, 2021
Patterning material film stack with metal-containing top coat for enhanced sensitivity in extreme ultraviolet (EUV) lithography
IBM0 citations62
US11133195B2Sep 28, 2021
Inverse tone pillar printing method using polymer brush grafts
IBM0 citations62
Showing the top 50 of 89 patents by PatentIndex Score.