Inventor

LEE TZE-LIANG

TW313 patents

⚠️ This page may combine multiple inventors who share the name “LEE TZE-LIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE TZE-LIANG

TAIWAN SEMICONDUCTOR MFG

FinFET with bottom SiGe layer in source/drain

Structure and method for semiconductor device

MOS devices with partial stressor channel

Semiconductor device and method of making the same

Integrated circuit devices, edge seals therefor

Method for selectively stressing MOSFETs to improve charge carrier mobility

Bonding pad and via structure design

Method for plasma treating and plasma nitriding gate oxides

MOS devices with partial stressor channel

Bump pad design for flip chip bumping

Method for forming copper pad redistribution and device formed

Method of protecting a copper pad structure during a fuse opening procedure

Headless CMP process for oxide planarization

Epitaxy silicon on insulator (ESOI)

Source/drain strained layers

Super anneal for process induced strain modulation

Strained transistor with hybrid-strain inducing layer

Bonding pad metal layer geometry design

Method of forming a nitride gate dielectric layer for advanced CMOS devices

Hybrid process for forming metal gates

SiGe selective growth without a hard mask

Method of forming a locally strained transistor

Selective nitride liner formation for shallow trench isolation

Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration

Integrated process for fuse opening and passivation process for CU/LOW-K IMD

Method for manufacturing a thin gate dielectric layer for integrated circuit fabrication

Seal ring and die corner stress relief pattern design to protect against moisture and metallic impurities

MOS device having source and drain regions with embedded germanium-containing diffusion barrier

Semiconductor device and method of forming vertical structure

TAIWAN SEMICONDUCTOR MFG CO LTD

System and method for supplying a precursor for an atomic layer deposition (ALD) process

Via patterning using multiple photo multiple etch

Interconnect structure and method

Multi-patterning to form vias with straight profiles

Via patterning using multiple photo multiple etch

Photoresist layer surface treatment, cap layer, and method of forming photoresist pattern

Semiconductor device, FinFET device and methods of forming the same

Forming isolation regions for separating fins and gate stacks

Dielectric spacer to prevent contacting shorting

MOS devices having epitaxy regions with reduced facets

Treatment system and method

Treatment system and method

Interconnect structure and method

Semiconductor device and method

Fin structure of semiconductor device, manufacturing method thereof, and manufacturing method of active region of semiconductor device

FinFET with rounded source/drain profile

Germanium profile for channel strain

Selective etching in the formation of epitaxy regions in MOS devices

MOS devices with non-uniform P-type impurity profile

Source and drain stressors with recessed top surfaces

IND TECH RES INST

Fabrication process for copper structures