Inventor

KRUCKEMYER DAVID A

US32 patents

⚠️ This page may combine multiple inventors who share the name “KRUCKEMYER DAVID A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KRUCKEMYER DAVID A

BROADCOM CORP

Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent

Clock gating of sub-circuits within a processor execution unit responsive to instruction latency counter within processor issue circuit

Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent

Inhibiting of a co-issuing instruction in a processor having different pipeline lengths

Link and fall-through address formation using a program counter portion selected by a specific branch address bit

Method for cancelling conditional delay slot instructions

Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboard

Selection of link and fall-through address using a bit in a branch address for the selection

Method for cancelling speculative conditional delay slot instructions

Method for identifying basic blocks with conditional delay slot instructions

Use of tags to cancel a conditional branch delay slot instruction

Method for identifying basic blocks with conditional delay slot instructions

ARTERIS INC

System and method for adaptation of coherence models between agents

Compression of hardware cache coherent addresses

Method for using victim buffer in cache coherent systems

Configurable snoop filters for cache coherent systems

Configurable snoop filters for cache coherent systems

Cache coherent system implementing victim buffers

Victim buffer for cache coherent systems

AZUL SYSTEMS INC

Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines

Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag

Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system

ASHCRAFT MATTHEW W

Outstanding load miss buffer with shared entries

Load store unit with load miss result buffer

Load miss result buffer with shared data lines

SILICON GRAPHICS INT CORP

System and method for ordering of data transferred over multiple channels

System and method for ordering of data transferred over multiple channels

KRUCKEMYER DAVID A

Multi-level store merging in a cache and memory hierarchy

Proxy cache conditional allocation

SILICON GRAPHICS INC

System and method for ordering of data transferred over multiple channels

MARTIN RANDAL G

System and method for ordering of data transferred over multiple channels

VENTANA MICRO SYSTEMS INC

Method and apparatus for deskewing die to die communication between system on chip devices