Method and apparatus for deskewing die to die communication between system on chip devices

Abstract

A die-to-die (D2D) interface between chiplets of a system on a chip (SoC) in which each of the chiplets are subdivided into slices. The D2D interface includes a transmission interface coupled between first and second chiplets, which includes a first transmission path for a first slice and a second transmission path for a second slice. The first chiplet includes receive circuitry which further includes a write interface and a read interface. The write interface stores data received from the first transmission path into a first FIFO using a first clock signal received via the first transmission path, and stores data received from the second transmission path into a second FIFO using a second clock signal received via the second transmission path. The read interface reads data stored in the first and second FIFOs using the first clock signal. The first and second transmission paths may be subject to different delays.

The invention claimed is: 
     
         1 . A die-to-die (D2D) interface between a plurality of chiplets of a system on a chip (SoC), in which each of the chiplets are subdivided into a plurality of slices, the D2D interface comprising:
 a transmission interface coupled between first and second chiplets comprising a first transmission path for a first slice and a second transmission path for a second slice; and   the first chiplet comprising receive circuitry, the receive circuitry comprising:
 a write interface that stores data received from the first transmission path into a first first-in, first out (FIFO) using a first clock signal received via the first transmission path, and that stores data received from the second transmission path into a second FIFO using a second clock signal received via the second transmission path; and 
 a read interface that reads data stored in the first and second FIFOs by clocking the data out using the first clock signal. 
   
     
     
         2 . The D2D interface of  claim 1 , wherein the first and second transmission paths of the transmission interface are subject to different delays. 
     
     
         3 . The D2D interface of  claim 1 , wherein the receive circuitry comprises:
 a first write counter that provides a first write pointer to the first FIFO, wherein the first write counter has a clock input receiving the first clock signal;   a first read counter that provides a first read pointer to the first FIFO, wherein the first read counter has a clock input receiving the first clock signal;   a second write counter that provides a second write pointer to the second FIFO, wherein the second write counter has a clock input receiving the second clock signal; and   a second read counter that provides a second read pointer to the second FIFO, wherein the second read counter has a clock input receiving the first clock signal.   
     
     
         4 . The D2D interface of  claim 3 , further comprising a skew controller with a comparator that is configured to compare a first sample of first data from the first FIFO pointed to by the first read pointer with a second sample of the duplicate first data from the second FIFO pointed to by the second read pointer to determine skew adjustment. 
     
     
         5 . The D2D interface of  claim 4 , further comprising nudge logic that is configured to delay the second read pointer when the comparison indicates that second FIFO is ahead of the first FIFO. 
     
     
         6 . The D2D interface of  claim 4 , further comprising nudge logic that is configured to delay the first read pointer when the comparison indicates that the first FIFO is ahead of the second FIFO. 
     
     
         7 . The D2D interface of  claim 4 , wherein the first data and the duplicate first data each comprise incremental training data values indicative of clock cycle transitions, further comprising nudge logic that is configured to delay one of the first and second read pointers by a number of clock cycles based on a difference between the first and second samples. 
     
     
         8 . A method of transferring data in a die-to-die (D2D) interface between a plurality of chiplets of a system on a chip (SoC), wherein each of the chiplets are subdivided into a plurality of slices, and wherein the D2D interface includes a transmission interface coupled between first and second chiplets comprising a first transmission path for a first slice and a second transmission path for a second slice, the method comprising:
 storing data received from the first transmission path into a first first-in, first out (FIFO) using a first clock signal received via the first transmission path;   storing data received from the second transmission path into a second FIFO using a second clock signal received via the second transmission path;   reading data stored in the first FIFO by clocking the data out using the first clock signal; and   reading data stored in the second FIFO by clocking the data out using the first clock signal.   
     
     
         9 . The method of  claim 8 , wherein the first and second transmission paths of the transmission interface are subject to different delays. 
     
     
         10 . The method of  claim 8 , further comprising:
 providing a first write counter for providing a first write pointer to the first FIFO, wherein the first write counter has a clock input receiving the first clock signal;   providing a first read counter for providing a first read pointer to the first FIFO, wherein the first read counter has a clock input receiving the first clock signal;   providing a second write counter for providing a second write pointer to the second FIFO, wherein the second write counter has a clock input receiving the second clock signal; and   providing a second read counter for providing a second read pointer to the second FIFO, wherein the second read counter has a clock input receiving the first clock signal.   
     
     
         11 . The method of  claim 10 , further comprising determining skew adjustment by comparing a first sample of first data from the first FIFO pointed to by the first read pointer with a second sample of the duplicate first data from the second FIFO pointed to by the second read pointer. 
     
     
         12 . The method of  claim 11 , further comprising delaying the second read pointer when the comparing indicates that second FIFO is ahead of the first FIFO. 
     
     
         13 . The method of  claim 11 , further delaying the first read pointer when the comparing indicates that the first FIFO is ahead of the second FIFO. 
     
     
         14 . The method of  claim 11 , further comprising:
 transmitting duplicate incremental training data values indicative of clock cycle transitions across the first and second transmission paths, wherein the first data and the duplicate first data comprise duplicate incremental training data values; and   delaying one of the first and second read pointers by a number of clock cycles based on a difference between the first and second samples.   
     
     
         15 . A die-to-die (D2D) interface between a plurality of chiplets of a system on a chip (SoC), in which each of the chiplets are subdivided into a plurality of slices, the D2D interface comprising:
 a transmission interface coupled between first and second chiplets comprising a first transmission path for a first slice and a second transmission path for a second slice; and   the first chiplet comprising receive circuitry, the receive circuitry comprising:
 a first write interface that stores data received from the first transmission path into a first first-in, first out (FIFO) using a first clock signal received via the first transmission path; 
 a second write interface that stores data received from the second transmission path into a second FIFO using a second clock signal received via the second transmission path; 
 a first read interface that reads data stored in the first FIFO by clocking the data out using the first clock signal; and 
 a second read interface that reads data stored in the second FIFO by clocking the data out using the first clock signal. 
   
     
     
         16 . The D2D interface of  claim 15 , wherein the first and second transmission paths of the transmission interface are subject to different delays. 
     
     
         17 . The D2D interface of  claim 15 , wherein the receive circuitry comprises:
 a first write counter that provides a first write pointer to the first FIFO, wherein the first write counter has a clock input receiving the first clock signal;   a first read counter that provides a first read pointer to the first FIFO, wherein the first read counter has a clock input receiving the first clock signal;   a second write counter that provides a second write pointer to the second FIFO, wherein the second write counter has a clock input receiving the second clock signal; and   a second read counter that provides a second read pointer to the second FIFO, wherein the second read counter has a clock input receiving the first clock signal.   
     
     
         18 . The D2D interface of  claim 17 , further comprising a skew controller with a comparator that is configured to determine skew adjustment by comparing a first sample of first data from the first FIFO pointed to by the first read pointer with a second sample of the duplicate first data from the second FIFO pointed to by the second read pointer. 
     
     
         19 . The D2D interface of  claim 18 , further comprising nudge logic that is configured to delay the second read pointer when the comparison indicates that second FIFO is ahead of the first FIFO and to delay the first read pointer when the comparison indicates that the first FIFO is ahead of the second FIFO. 
     
     
         20 . The D2D interface of  claim 18 , wherein the first data and the duplicate first data each comprise incremental training data values indicative of clock cycle transitions, further comprising nudge logic that is configured to delay one of the first and second read pointers by a number of clock cycles based on a difference between the first and second samples.