Inventor

REDDY SRINIVAS T

US72 patents

⚠️ This page may combine multiple inventors who share the name “REDDY SRINIVAS T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

REDDY SRINIVAS T

ALTERA CORP

Programmable logic device architecture with super-regions having logic regions and a memory region

Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits

Programmable logic array integrated circuit devices with interleaved logic array blocks

Programmable logic array integrated circuit devices

Programmable logic device having embedded dual-port random access memory configurable as single-port memory

Programmable logic device memory array circuit having combinable single-port memory arrays

Redundancy circuitry for programmable logic devices with interleaved input circuits

Circuitry and methods for internal interconnection of programmable logic devices

Programmable logic device circuitry for improving multiplier speed and/or efficiency

Dual-port programmable logic device variable depth and width memory array

Programmable logic device architectures

Implementation of redundancy on a programmable logic device

Programmable logic array integrated circuit devices

Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits

Programmable logic device with hierarchical interconnection resources

Programmable logic device with redundant circuitry

Programmable logic device with redundant circuitry

Programmable logic array integrated circuit devices

Input/output interface circuitry for programmable logic array integrated circuit devices

Programmable logic device with hierarchical interconnection resources

Programmable logic array intergrated circuit devices

Variable-path-length voltage-controlled oscillator circuit

Input/output interface circuitry for programmable logic array integrated circuit devices

Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices

Programmable logic devices with spare circuits for replacement of defects

Configurable memory structures in a programmable logic device

Techniques for programming programmable logic array devices

Programmable logic array integrated circuit architectures

Look-up table using multi-level decode

Programmable logic device with low power voltage level translator

Reduced noise output buffer

Routing architecture for a programmable logic device

Programmable logic device with hierarchical interconnection resources

Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits

Redundancy circuitry for programmable logic devices with interleaved input circuits

Programmable logic device circuitry for improving multiplier speed and/or efficiency

Programmable logic device with hierarchical interconnection resources

Programmable logic device memory array circuit having combinable single-port memory arrays

Techniques for programming programmable logic array devices

Input/output circuitry for programmable logic devices

Programmable logic devices with spare circuits for replacement of defects

Reducing false positives in configuration error detection for programmable devices

Multiple size memories in a programmable logic device

Routing architecture for a programmable logic device

Redundancy circuitry for programmable logic devices with interleaved input circuits

Techniques for programming programmable logic array devices

Programmable logic array integrated circuit devices

Programmable logic array integrated circuit devices

Look-up table using multi-level decode

ALTERA CORP SAN JOSE CA

Multifunction memory array in a programmable logic device