Inventor

SEEMAN THOMAS R

US15 patents

⚠️ This page may combine multiple inventors who share the name “SEEMAN THOMAS R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COMPAQ COMPUTER CORP

9 patents

US5870567AFeb 9, 1999

Lock protocol for PCI bus using an additional "superlock" signal on the system bus

COMPAQ COMPUTER CORP50 citations92

US6085274AJul 4, 2000

Computer system with bridges having posted memory write buffers

COMPAQ COMPUTER CORP22 citations92

US5881253AMar 9, 1999

Computer system using posted memory write buffers in a bridge to implement system management mode

COMPAQ COMPUTER CORP29 citations92

US5832243ANov 3, 1998

Computer system implementing a stop clock acknowledge special cycle

COMPAQ COMPUTER CORP20 citations92

US5659789AAug 19, 1997

Stopclock toggle system for powering two CPUs from a regulator only sized for one CPU

COMPAQ COMPUTER CORP18 citations84

SRC COMPUTERS INC

5 patents

US7565461B2Jul 21, 2009

Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers

SRC COMPUTERS INC20 citations92

US7373440B2May 13, 2008

Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format

SRC COMPUTERS INC23 citations92

US7003593B2Feb 21, 2006

Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port

SRC COMPUTERS INC24 citations92

US7421524B2Sep 2, 2008

Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format

SRC COMPUTERS INC9 citations83

US7197575B2Mar 27, 2007

Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers

SRC COMPUTERS INC16 citations83

COMPAQ INFORMATION TECHNOLOGIE

1 patent

US6449677B1Sep 10, 2002

Method and apparatus for multiplexing and demultiplexing addresses of registered peripheral interconnect apparatus

COMPAQ INFORMATION TECHNOLOGIE40 citations91

SEEMAN THOMAS R

COMPAQ COMPUTER CORP

Delayed transaction protocol for computer system bus

Bus-to-bus bridge in computer system, with fast burst memory range

Bus-to-bus bridge in computer system, with fast burst memory range

Bus-to-bus bridge in computer system, with fast burst memory range

Lock protocol for PCI bus using an additional &#34;superlock&#34; signal on the system bus

Computer system with bridges having posted memory write buffers

Computer system using posted memory write buffers in a bridge to implement system management mode

Computer system implementing a stop clock acknowledge special cycle

Stopclock toggle system for powering two CPUs from a regulator only sized for one CPU

SRC COMPUTERS INC

Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers

Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format

Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port

Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format

Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers

COMPAQ INFORMATION TECHNOLOGIE

Method and apparatus for multiplexing and demultiplexing addresses of registered peripheral interconnect apparatus

Lock protocol for PCI bus using an additional "superlock" signal on the system bus