Bus-to-bus bridge in computer system, with fast burst memory range

Abstract

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches a bridge interface from the PCI bus, and it is recognized that the address is within the fast burst range, then the fast burst mode is allowed, and write or read requests can be issued without waiting for the snoop phase, since there is no possibility of defer or retry.

What is claimed is:  
     
       1. A method of operating a computer system of the type having a CPU with a system bus coupled to the CPU, a main memory coupled to said system bus, and having an expansion bus coupled to the system bus by a bridge, comprising the steps of: 
       initiating by said CPU a transaction on said system bus directed to a device coupled to said expansion bus, said transaction being initiated by a request being applied to said system bus by said CPU, followed by a snoop phase and a response phase  
       defining a range of main memory addresses to which transactions are completed in order without being deferred or retried; 
       initiating at least first and second transactions on said system bus directed to said range of main memory addresses, said transactions being initiated by a first request being applied to said system bus, followed immediately by a second request, without waiting for a snoop phase.  
     
     
       2. A method according to  claim 1  wherein said expansion bus is a standardized “PCI” bus. 
     
     
       3. A method according to  claim 2  wherein said CPU is a microprocessor of the “Pentium Pro” type. 
     
     
       4. A method according to  claim 1  including the step of designating a  said range of memory as a fast burst memory region and initiating a pair of  to which transactions may be addressed consecutively and completed in order, without waiting for a snoop phase, when said first transaction is addressed to said range  between said memory transactions. 
     
     
       5. A method according to  claim 4  wherein said fast burst memory region includes the range of addresses of said main memory above  1  Megabyte. 
     
     
       6. A method according to  claim 1  wherein said CPU initiated transactions may include a retry or deferred responseand said first transaction may not include a retry or deferred response . 
     
     
       7. A computer system, comprising: 
       a CPU;  
       a system bus coupled to the CPU;  
       a main memory coupled to said system bus;  
       an expansion bus coupled to the system bus by a bridge;  
       a signal path element of said system bus for initiating by said CPU a transaction on said system bus directed to a device coupled to said expansion bus, said transaction being initiated by a request being applied to said system bus by said CPU, followed by a snoop phase;  
       said signal path element also providing for initiating at least first and second transactions on said system bus directed to a defined range of addresses of said main memory to which transactions are completed in order without being deferred or retried, said first transaction being initiated by a first request being applied to said system bus, followed immediately by a second request, without waiting for a snoop phase.  
     
     
       8. A system according to  claim 7  wherein said defined range of addresses comprises a fast burst memory range is defined by information stored in said bridge and said path element adapted to begin said second transaction without waiting for said snoop phase of said first transaction when said first transaction is directed to said defined range of addresses. 
     
     
       9. A system according to  claim 8  wherein said first and second transactions are initiated by said bridge. 
     
     
       10. A system according to  claim 7  wherein said expansion bus is a standardized “PCI” bus. 
     
     
       11. A system according to  claim 10  wherein said CPU is a microprocessor of the “Pentium Pro” type. 
     
     
       12. A system according to  claim 7 , wherein said defined range of addresses includes the range of addresses of said main memory above  1  Megabyte. 
     
     
       13. A system according to  claim 7 , wherein said defined range of addresses of said main memory comprises a fast burst memory range to which successive transactions may be addressed and completed in order without waiting for snoop phases between said memory transactions.