Inventor · disambiguated record
Thomas R. Seeman
Also filed as: SEEMAN THOMAS R
15 granted patents·2 pending applications·535 citations·filing 1995–2012
95Inventor score
Files withCOMPAQ COMPUTER CORP9SRC COMPUTERS INC5BURTON LEE A1COMPAQ INFORMATION TECHNOLOGIE1HUPPENTHAL JON M1
Top patents by PatentIndex Score
17 records- 0189USRE37980EBus-to-bus bridge in computer system, with fast burst memory rangeCOMPAQ COMPUTER CORP·Filed 2000·Granted Feb 4, 2003·44 cites·13 claims
- 0288US7565461B2Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllersSRC COMPUTERS INC·Filed 2005·Granted Jul 21, 2009·20 cites·24 claims
- 0385US5870567ADelayed transaction protocol for computer system busCOMPAQ COMPUTER CORP·Filed 1996·Granted Feb 9, 1999·121 cites·16 claims
- 0481US5835741ABus-to-bus bridge in computer system, with fast burst memory rangeCOMPAQ COMPUTER CORP·Filed 1996·Granted Nov 10, 1998·73 cites·11 claims
- 0578US7373440B2Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module formatSRC COMPUTERS INC·Filed 2001·Granted May 13, 2008·23 cites·24 claims
- 0677US7003593B2Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface portSRC COMPUTERS INC·Filed 2002·Granted Feb 21, 2006·24 cites·38 claims
- 0771US7197575B2Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllersSRC COMPUTERS INC·Filed 2003·Granted Mar 27, 2007·16 cites·51 claims
- 0867US6098134ALock protocol for PCI bus using an additional "superlock" signal on the system busCOMPAQ COMPUTER CORP·Filed 1996·Granted Aug 1, 2000·50 cites·11 claims
- 0966US7421524B2Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module formatSRC COMPUTERS INC·Filed 2004·Granted Sep 2, 2008·9 cites·15 claims
- 1062US6449677B1Method and apparatus for multiplexing and demultiplexing addresses of registered peripheral interconnect apparatusCOMPAQ INFORMATION TECHNOLOGIE·Filed 1999·Granted Sep 10, 2002·40 cites·35 claims
- 1158US6148359ABus-to-bus bridge in computer system, with fast burst memory rangeCOMPAQ COMPUTER CORP·Filed 1998·Granted Nov 14, 2000·26 cites·22 claims
- 1258US5881253AComputer system using posted memory write buffers in a bridge to implement system management modeCOMPAQ COMPUTER CORP·Filed 1996·Granted Mar 9, 1999·29 cites·8 claims
- 1352US6085274AComputer system with bridges having posted memory write buffersCOMPAQ COMPUTER CORP·Filed 1999·Granted Jul 4, 2000·22 cites·17 claims
- 1448US5832243AComputer system implementing a stop clock acknowledge special cycleCOMPAQ COMPUTER CORP·Filed 1996·Granted Nov 3, 1998·20 cites·10 claims
- 1545US5659789AStopclock toggle system for powering two CPUs from a regulator only sized for one CPUCOMPAQ COMPUTER CORP·Filed 1995·Granted Aug 19, 1997·18 cites·26 claims
- 1641US2012117318A1Heterogeneous computing system comprising a switch/network adapter port interface utilizing load-reduced dual in-line memory modules (lr-dimms) incorporating isolation memory buffersBURTON LEE A·Filed 2011·Application pending·0 cites
- 1739US2013157639A1Mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumptionHUPPENTHAL JON M·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →