Inventor

HENSON WILLIAM K

US55 patents

⚠️ This page may combine multiple inventors who share the name “HENSON WILLIAM K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HENSON WILLIAM K

IBM

Semiconductor device having dual metal gates and method of manufacture

Method of providing threshold voltage adjustment through gate dielectric stack modification

Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer

High performance stress-enhance MOSFET and method of manufacture

Stress engineering using dual pad nitride with selective SOI device architecture

High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods

eFuse containing SiGe stack

eFuse with partial SiGe layer and design structure therefor

Method of forming a resistor and an FET from the metal portion of a MOSFET metal gate stack

Disposable metallic or semiconductor gate spacer

High performance stress-enhance MOSFET and method of manufacture

Formation of improved SOI substrates using bulk semiconductor wafers

Fully silicided gate electrodes and method of making the same

CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETs

Semiconductor structure for low parasitic gate capacitance

Single crystal fuse on air in bulk silicon

Scalable strained FET device and method of fabricating the same

Structure and method for using high-K material as an etch stop layer in dual stress layer process

High-K metal gate CMOS

Electrical fuse having a fully silicided fuselink and enhanced flux divergence

Residue free patterned layer formation method applicable to CMOS structures

Electrical fuse having a fully silicided fuselink and enhanced flux divergence

Semiconductor structure with enhanced performance using a simplified dual stress liner configuration

Silicide gate field effect transistors and methods for fabrication thereof

Stressed SOI FET having tensile and compressive device regions

High performance stress-enhance MOSFET and method of manufacture

Dual metal integration scheme based on full silicidation of the gate electrode

Stress engineering using dual pad nitride with selective SOI device architecture

Electrical fuse with a thinned fuselink middle portion

Metal gate stack and semiconductor gate stack for CMOS devices

Work function adjustment by carbon implant in semiconductor devices including gate structure

Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor

Method and structure for work function engineering in transistors including a high dielectric constant gate insulator and metal gate (HKMG)

Formation of improved SOI substrates using bulk semiconductor wafers

After gate fabrication of field effect transistor having tensile and compressive regions

Low resistance contact semiconductor device structure

CHUDZIK MICHAEL P

Method and structure for gate height scaling with high-k/metal gate technology

Method and structure for gate height scaling with high-k/metal gate technology

High-K dielectric and metal gate stack with minimal overlap with isolation region

Method and structure for work function engineering in transistors including a high dielectric constant gate insulator and metal gate (HKMG)

GREENE BRIAN J

Threshold voltage adjustment through gate dielectric stack modification

Self-aligned embedded SiGe structure and method of manufacturing the same

Self-aligned embedded SiGe structure and method of manufacturing the same

HENSON WILLIAM K

Structure and method for using high-k material as an etch stop layer in dual stress layer process

Formation of improved SOI substrates using bulk semiconductor wafers

KIM DEOK-KEE

Efuse containing sige stack

RIM KERN

Method and structure for pFET junction profile with SiGe channel

MO RENEE T

High-K metal gate CMOS

BRODSKY MARYJANE

Threshold voltage adjustment for thin body MOSFETs

BU HUIMING

High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof