Self-aligned embedded SiGe structure and method of manufacturing the same

Abstract

A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

1. A semiconductor structure comprising:
 a gate stack located on a top surface of a semiconductor layer in a semiconductor substrate, said semiconductor layer comprising a first single-crystalline semiconductor material; and 
 a pair of embedded semiconductor material portions embedded in said semiconductor layer and comprising a second single-crystalline semiconductor material that is epitaxially aligned with, and lattice mismatched with, said first single-crystalline semiconductor material, wherein each of said pair of embedded semiconductor material portions has a slanted planar interface between a first depth from a top surface of said semiconductor layer into said semiconductor substrate and a second depth from said top surface into said semiconductor substrate, said second depth being greater than said first depth. 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein each of said pair of embedded semiconductor material portions has a substantially vertical interface with said semiconductor layer between said top surface and said first depth, and a substantially horizontal interface with said semiconductor layer at said second depth. 
     
     
       3. The semiconductor structure of  claim 1 , wherein said first single-crystalline semiconductor material is silicon, and said second single-crystalline semiconductor material is a silicon-germanium alloy. 
     
     
       4. The semiconductor structure of  claim 1 , wherein said first single-crystalline semiconductor material is silicon, and said second single-crystalline semiconductor material is a silicon-carbon alloy. 
     
     
       5. The semiconductor structure of  claim 1 , wherein said gate stack includes, from bottom to top, a gate dielectric and a gate electrode, said semiconductor structure is a field effect transistor having a channel comprising a portion of said semiconductor layer directly underneath said gate dielectric, said channel having a doping of a first conductivity type, and an entirety of each of said pair of embedded semiconductor material portions has a doping of a second conductivity type that is the opposite of said first conductivity type. 
     
     
       6. The semiconductor structure of  claim 5 , further comprising:
 a source-side extension region comprising said first single-crystal semiconductor material and having a doping of said second conductivity type and contacting a source-side embedded semiconductor material portion among said pair of embedded semiconductor material portions; and 
 a drain-side extension region comprising said first single-crystal semiconductor material and having a doping of said second conductivity type and contacting a drain-side embedded semiconductor material portion among said pair of embedded semiconductor material portions. 
 
     
     
       7. The semiconductor structure of  claim 5 , further comprising:
 a source-side metal-semiconductor alloy portion located on a source-side embedded semiconductor material portion among said pair of embedded semiconductor material portions, wherein an interface between a proximal portion of said source-side metal-semiconductor alloy portion and said source-side embedded semiconductor material portion is a first planar surface that is located between said top surface of said semiconductor layer and said first depth; and 
 a drain-side metal-semiconductor alloy portion located on a drain-side embedded semiconductor material portion among said pair of embedded semiconductor material portions, wherein an interface between a proximal portion of said drain-side metal-semiconductor alloy portion and said drain-side embedded semiconductor material portion is a second planar surface that is located between said top surface of said semiconductor layer and said first depth. 
 
     
     
       8. The semiconductor structure of  claim 1 , wherein said gate stack includes, from bottom to top, a gate dielectric and a gate electrode, said semiconductor structure is a field effect transistor having a channel comprising a portion of said semiconductor layer directly underneath said gate dielectric, said channel having a doping of a first conductivity type, and each of a deep source region and a deep drain region of said field effect transistor includes an upper portion comprising said second single-crystalline semiconductor material and having a doping of a second conductivity type and a lower portion comprising said first single-crystalline semiconductor material and having a doping of said second conductivity type, wherein said second conductivity type is the opposite of said first conductivity type. 
     
     
       9. The semiconductor structure of  claim 8 , further comprising:
 a first source-side extension region portion comprising said first single-crystal semiconductor material and having a doping of said second conductivity type and contacting one side of said channel; 
 a second source-side extension region portion comprising said second single-crystal semiconductor material and having a doping of said second conductivity type and contacting a source-side embedded semiconductor material portion among said pair of embedded semiconductor material portions; 
 a first drain-side extension region portion comprising said first single-crystal semiconductor material and having a doping of said second conductivity type and contacting another side of said channel; and 
 a second drain-side extension region portion comprising said second single-crystal semiconductor material and having a doping of said second conductivity type and contacting a drain-side embedded semiconductor material portion among said pair of embedded semiconductor material portions. 
 
     
     
       10. The semiconductor structure of  claim 9 , further comprising:
 a source-side semiconductor material portion comprising said second single-crystal semiconductor material and contacting said second source-side extension region portion and said deep source region; wherein said source-side semiconductor material portion has a doping of said first conductivity type or undoped; and 
 a drain-side semiconductor material portion comprising said second single-crystal semiconductor material and contacting said second drain-side extension region portion and said deep drain region; wherein said drain-side semiconductor material portion has a doping of said first conductivity type or undoped. 
 
     
     
       11. The semiconductor structure of  claim 8 , further comprising:
 a source-side metal-semiconductor alloy portion located on said deep source region, wherein an interface between a proximal portion of said source-side metal-semiconductor alloy portion and said deep source region is a first planar surface that is located between said top surface of said semiconductor layer and said first depth; and 
 a drain-side metal-semiconductor alloy portion located on said deep drain region, wherein an interface between a proximal portion of said drain-side metal-semiconductor alloy portion and said deep drain region is a second planar surface that is located between said top surface of said semiconductor layer and said first depth.