Inventor

GREENE BRIAN J

US77 patents

⚠️ This page may combine multiple inventors who share the name “GREENE BRIAN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GREENE BRIAN J

IBM

Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions

Merged fin structures for finFET devices

Method of providing threshold voltage adjustment through gate dielectric stack modification

Dual metal gate finFETs with single or dual high-K gate dielectric

Transistor having V-shaped embedded stressor

FinFET structure and method to adjust threshold voltage in a FinFET structure

Method and apparatus for post silicide spacer removal

Method to reduce contact resistance on thin silicon-on-insulator device

Structure and method for improved stress and yield in pFETS with embedded SiGe source/drain regions

Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost

Semiconductor devices with rotated substrates and methods of manufacture thereof

Method and structure for improving device performance variation in dual stress liner technology

Method and structure to reduce contact resistance on thin silicon-on-insulator device

Scalable strained FET device and method of fabricating the same

Method and structure for improving device performance variation in dual stress liner technology

Multi-height multi-composition semiconductor fins

Dummy gate interconnect for semiconductor device

Fin-shaped field effect transistor (finFET) structures having multiple threshold voltages (Vt) and method of forming

FinFET with constrained source-drain epitaxial region

Tucked active region without dummy poly for performance boost and variation reduction

FinFET structure and method to adjust threshold voltage in a FinFET structure

Anticipatory implant for TSV

MOS having a sic/sige alloy stack

Transistor with dielectric stressor elements

Transistor with dielectric stressor element fully underlying the active semiconductor region

Method and structure for reducing induced mechanical stresses

Method of forming channel region dopant control in fin field effect transistor

Methods for forming high performance gates and structures thereof

Implant after through-silicon via (TSV) etch to getter mobile ions

GLOBALFOUNDRIES INC

Merged source drain epitaxy

Device with decreased pitch contact to active regions

Fin fabrication process with dual shallow trench isolation and tunable inner and outer fin profile

Method and IC structure for increasing pitch between gates

Epitaxial growth of material on source/drain regions of FinFET structure

GREENE BRIAN J

Threshold voltage adjustment through gate dielectric stack modification

Creating anisotropically diffused junctions in field effect transistor devices

Self-aligned embedded SiGe structure and method of manufacturing the same

Self-aligned embedded SiGe structure and method of manufacturing the same

GLOBALFOUNDRIES US INC

Source/drain contact depth control

Stacked-gate transistors

SAMSUNG ELECTRONICS CO LTD

Test structure of semiconductor device

Test structure of semiconductor device

DENNARD ROBERT H

Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage

ZHU HUILONG

Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same

CHIDAMBARRAO DURESETI

CMOS having a SiC/SiGe alloy stack

YU XIAOJUN

Tucked active region without dummy poly for performance boost and variation reduction

CARTIER EDUARD A

FinFET structure and method to adjust threshold voltage in a FinFET structure

INFINEON TECHNOLOGIES AG

Methods of manufacturing semiconductor devices with rotated substrates

CHEN XIANGDONG

Field effect device including recessed and aligned germanium containing channel

FANG SUNFEI

Structure and method to improve threshold voltage of MOSFETS including a high K dielectric