Inventor

PAL ROHIT

US45 patents

⚠️ This page may combine multiple inventors who share the name “PAL ROHIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAL ROHIT

GLOBALFOUNDRIES INC

Integrated circuit having multiple threshold voltages

Threshold voltage control for mixed-type non-planar semiconductor devices

Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods

Methods for fabricating MOS devices having epitaxially grown stress-inducing source and drain regions

Threshold voltage control for mixed-type non-planar semiconductor devices

Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same

Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods

Transistor device having asymmetric embedded strain elements and related manufacturing method

Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits

Spacer defined fin growth and differential fin width

Semiconductor transistor device structure with back side source/drain contact plugs, and related manufacturing method

Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods

Replacement low-K spacer

Method of forming stepped recesses for embedded strain elements in a semiconductor device

Gate height uniformity in semiconductor devices

Gate height uniformity in semiconductor devices

Methods for calibrating a process for growing an epitaxial silicon film and methods for growing an epitaxial silicon film

PAL ROHIT

Transistor device having asymmetric embedded strain elements and related manufacturing method

Method of manufacturing a transistor device having asymmetric embedded strain elements

Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods

Formation of a channel semiconductor alloy by forming a nitride based hard mask layer

Fabrication of semiconductors with high-K/metal gate electrodes

Fabrication of semiconductors with high-K/metal gate electrodes

High-K metal gate electrode structures formed by early cap layer adaptation

Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods

Methods for protecting film layers while removing hardmasks during fabrication of semiconductor devices

ADVANCED MICRO DEVICES INC

Stress enhanced MOS transistor and methods for its fabrication

Methods for fabricating MOS devices having highly stressed channels

Semiconductor devices having faceted silicide contacts, and related fabrication methods

Stress enhanced transistor and methods for its fabrication

Method of controlling embedded material/gate proximity

Stress enhanced transistor

UNIV MICHIGAN

Thermal micro-valves for micro-integrated devices

Reconfigurable microactuator and method of configuring same

CARTER RICHARD

Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization

Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization

GREENE BRIAN J

Self-aligned embedded SiGe structure and method of manufacturing the same

Self-aligned embedded SiGe structure and method of manufacturing the same

NG MAN FAI

Gate etch optimization through silicon dopant profile change

Gate etch optimization through silicon dopant profile change

YANG FRANK BIN

Methods for fabricating MOS devices having highly stressed channels

YANG BIN

Semiconductor transistor device structure with back side gate contact plugs, and related manufacturing method

HUA ZHISHAN

Reconfigurable microactuator and method of configuring same

KRONHOLZ STEPHAN

Formation of a channel semiconductor alloy by a nitride hard mask layer and an oxide mask

KRONHOLZ STEPHAN-DETLEF

Transistors with embedded strain-inducing material formed in cavities provided by an oxidizing etch process