Inventor

HASAN MOHAMMAD

US16 patents

⚠️ This page may combine multiple inventors who share the name “HASAN MOHAMMAD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

15 patents

US11804523B2Oct 31, 2023

Integrated circuit structures with backside gate partial cut or trench contact partial cut

INTEL CORP0 citations62

US12527078B2Jan 13, 2026

Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation

INTEL CORP0 citations61

US12507464B2Dec 23, 2025

Gate aligned fin cut for advanced integrated circuit structure fabrication

INTEL CORP0 citations60

US12288808B2Apr 29, 2025

High aspect ratio source or drain structures with abrupt dopant profile

INTEL CORP0 citations60

US12575151B2Mar 10, 2026

Gate-all-around integrated circuit structures having doped subfin

INTEL CORP0 citations59

US12507449B2Dec 23, 2025

Gate-all-around integrated circuit structures having necked feature

INTEL CORP0 citations59

US12484207B2Nov 25, 2025

SRAM with channel count contrast for greater read stability

INTEL CORP0 citations59

US12457779B2Oct 28, 2025

Gate cut structures

INTEL CORP0 citations58

US12369392B2Jul 22, 2025

Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates

INTEL CORP0 citations58

US11990472B2May 21, 2024

Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates

INTEL CORP0 citations58

US12457778B2Oct 28, 2025

Conductive contacts wrapped around epitaxial source or drain regions

INTEL CORP0 citations57

US12176408B2Dec 24, 2024

Localized spacer for nanowire transistors and methods of fabrication

INTEL CORP1 citations57

IBM

1 patent

US7881937B2Feb 1, 2011

Method for analyzing patent claims

IBM32 citations92

HASAN MOHAMMAD

INTEL CORP

High aspect ratio source or drain structures with abrupt dopant profile

Integrated circuit structures having metal gates with tapered plugs

Deep etch processing for transistors having varying pitch

Integrated circuit structures with backside gate partial cut or trench contact partial cut

Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation

Gate aligned fin cut for advanced integrated circuit structure fabrication

High aspect ratio source or drain structures with abrupt dopant profile

Gate-all-around integrated circuit structures having doped subfin

Gate-all-around integrated circuit structures having necked feature

SRAM with channel count contrast for greater read stability

Gate cut structures

Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates

Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates

Conductive contacts wrapped around epitaxial source or drain regions

Localized spacer for nanowire transistors and methods of fabrication

IBM

Method for analyzing patent claims