Inventor

ANDREWS WILLIAM B

US31 patents

⚠️ This page may combine multiple inventors who share the name “ANDREWS WILLIAM B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANDREWS WILLIAM B

LATTICE SEMICONDUCTOR CORP

Multi-functional I/O buffers in a field programmable gate array (FPGA)

Double data rate input and output in a programmable logic device

Temperature-independent, linear on-chip termination resistance

Adaptive input logic for phase adjustments

Programmable I/O interfaces for FPGAs and other PLDs

Programmable signal termination for FPGAs and the like

Programmable logic devices with integrated standard-cell logic blocks

Programmable logic devices with integrated standard-cell logic blocks

Programmable current output and common-mode voltage buffer

Digitally controlled delay cells

Programmable level shifter

Programmable termination for single-ended and differential schemes

Programmable I/O interfaces for FPGAs and other PLDs

Dynamic over-voltage protection scheme for interface circuitry

Programmable current output buffer

Interface circuitry for electrical systems

Signal distribution scheme in field programmable gate array (FPGA) or field programmable system chip (FPSC) including cycle stealing units

Pre-configuration programmability of I/O circuitry

Hysteresis-based processing for applications such as signal bias monitors

Integrated circuit having independent voltage and process/temperature control

Dynamic over-voltage protection scheme for integrated-circuit devices

Programmable I/O structure for FPGAs and the like having reduced pad capacitance

Receiver for differential and reference voltage signaling with programmable common mode

Receiver for differential and reference-voltage signaling with programmable common mode

Programmable I/O structure for FPGAs and the like having shared circuitry

Temperature-independent, linear on-chip termination resistance

Output buffer with digital slew control

LUCENT TECHNOLOGIES INC

Hybrid programmable gate arrays

Signaling voltage range discriminator

Global signal distribution with reduced routing tracks in an FPGA

FPGA having predictable open-drain drive mode