Output buffer with digital slew control

Abstract

An improved output buffer having a digital output slew control and compensation for manufacturing process variations. Output slewing is accomplished by sequencing digital drive signals to paralleled output transistors. In one embodiment, a pre-driver sequences the drive signals by using the propagation delays of serially coupled digital logic gates to reduce power supply droop and/or ground bounce. The output transistors are turned off substantially simultaneously to avoid undesirable power supply DC current flow when the output buffer changes state. Programmably configuring the number of paralleled transistors that may be turned on at any given time allows a user to compensate for manufacturing process variations and determine the output impedance/drive capacity of the buffer.

1. A programmable logic device comprising an output buffer, the output buffer comprising:
 a first plurality of output transistors, each having a control terminal and two output terminals, wherein the first plurality of output transistors have paralleled output terminals connected between a first reference node and an output node; and 
 a first set of one or more pre-drivers, the first set adapted to generate a plurality of control signals, each control signal coupled to the control terminal of a corresponding output transistor of the first plurality of output transistors, the control signals being generated to sequentially turn on two or more of the first plurality of output transistors, wherein the first set of one or more pre-drivers is adapted to be programmably configured to operate in:
 a slew mode in which the control signals are generated to sequentially turn on two or more of the first plurality of output transistors; and 
 a non-slew mode in which the control signals are generated to turn on two or more of the first plurality of output transistors substantially simultaneously. 
 
 
   
   
     2. The device of  claim 1 , wherein the output buffer further comprises:
 a second plurality of output transistors, each having a control terminal and two output terminals, wherein the second plurality of output transistors have paralleled output terminals connected between a second reference node and the output node; and 
 a second set of one or more pre-drivers, the second set adapted to generate a plurality of control signals, each control signal coupled to the control terminal of a corresponding output transistor of the second plurality of output transistors, the control signals being generated to sequentially turn on two or more of the second plurality of output transistors. 
 
   
   
     3. The device of  claim 2 , wherein:
 the first reference node is a power-supply node; 
 the second reference node is ground; 
 the first set of one or more pre-drivers and the first plurality of output transistors correspond to one or more source slices of the output buffer; and 
 the second set of one or more pre-drivers and the second plurality of output transistors correspond to one or more sink slices of the output buffer. 
 
   
   
     4. The device of  claim 2 , wherein:
 the two or more of the second plurality of output transistors turn off substantially simultaneously at initiation of the sequentially turning on of the two or more of the first plurality of output transistors; and 
 the two or more of the first plurality of output transistors turn off substantially simultaneously at initiation of the sequentially turning on of the two or more of the second plurality of output transistors. 
 
   
   
     5. The device of  claim 1 , wherein:
 the first set of pre-drivers comprises two or more pre-drivers serially connected by one or more sequencing enable signals; and 
 each previous pre-driver controls the sequencing enable signal for the subsequent pre-driver to enable operations by the subsequent pre-driver only after the previous pre-driver has completed its operations. 
 
   
   
     6. The device of  claim 1 , wherein:
 associated with each pre-driver are two or more output transistors of the first plurality of output transistors; and 
 each pre-driver generates the corresponding control signals to sequentially turn on the associated two or more output transistors. 
 
   
   
     7. The device of  claim 1 , wherein the output buffer further comprises:
 a second plurality of output transistors, each having a control terminal and two output terminals, wherein the second plurality of output transistors have paralleled output terminals connected between a second reference node and the output node; and 
 a second set of one or more pre-drivers, the second set adapted to generate a plurality of control signals, each control signal coupled to the control terminal of a corresponding output transistor of the second plurality of output transistors, wherein the second set of one or more pre-drivers is adapted to be programmably configured to operate in:
 a slew mode in which the control signals are generated to sequentially turn on two or more of the second plurality of output transistors; and 
 a non-slew mode in which the control signals are generated to turn on two or more of the second plurality of output transistor substantially simultaneously. 
 
 
   
   
     8. The device of  claim 7 , wherein, in both the slew mode and the non-slew mode:
 the two or more of the second plurality of output transistors turn off substantially simultaneously at initiation of the turning on of the two or more of the first plurality of output transistors; and 
 the two or more of the first plurality of output transistors turn off substantially simultaneously at initiation of the turning on of the two or more of the second plurality of output transistors. 
 
   
   
     9. The device of  claim 1 , wherein:
 the first set of pre-drivers comprises two or more pre-drivers serially connected by one or more sequencing enable signals; and 
 in the slew mode, each previous pre-driver controls the sequencing enable signal for the subsequent pre-driver to enable operations by the subsequent pre-driver only after the previous pre-driver has completed its operations. 
 
   
   
     10. A programmable device comprising an output buffer, the output buffer comprising:
 at least two first-polarity output transistors, each output transistor having a control terminal and two output terminals, wherein the output terminals of the at least two first-polarity output transistors are coupled in parallel between a first node and an output node, the first node adapted to couple to a first power source; and 
 at least first and second pre-drivers, each pre-driver having at least first and second input nodes and at least first and second output nodes, each first output node coupling to a corresponding one of the control terminals of the two output transistors, the second input node of the second pre-driver being coupled to the second output node of the first pre-driver, and the first input node of the at least first and second pre-drivers being driven by a first input signal; 
 wherein the first and second pre-drivers are each adapted to be programmably configured to operate in:
 a non-slew mode in which an output signal is asserted on the first output node in response to the first input signal being asserted; and 
 a slew mode in which, in response to the first input signal on the first input node and an input signal on the second input node being concurrently asserted, an output signal is asserted on the first output node and an output signal is asserted the second output node, the assertion of the output signal on the second output node being delayed with respect to the assertion of the output signal on the first output node. 
 
 
   
   
     11. The device of  claim 10 , wherein the first and second pre-drivers are adapted to negate the output signals on the first output nodes substantially simultaneously after negation of the first input signal. 
   
   
     12. The device of  claim 11 , further comprising:
 at least two additional output transistors, each of the at least two additional transistors having two output terminals and a control terminal, wherein the output terminals of the at least two additional output transistors are coupled in parallel between the first node and an the output node; 
 wherein each pre-driver further comprises at least one additional input node and at least one additional output node, each additional output node coupling to a control terminal of the corresponding one of the at least two additional output transistors, each pre-driver asserting an output signal on the additional output node in response to the first input signal on the first input node and an input signal on the additional input node being concurrently asserted, and 
 wherein 1) if the at least first and second pre-drivers are in the slew mode, then the assertion of the output signal on the additional output node is delayed with respect to the assertion of the output signal on the first output node and 2) if the at least first and second pre-drivers are in the non-slew mode, then the output signal on the additional output node and the output signal on the first output node are asserted substantially simultaneously. 
 
   
   
     13. The device of  claim 12 , wherein if the at least first and second pre-drivers are operating in the slew mode, then the assertion of the output signal on the second output node is delayed with respect to the assertion of the output signal on the additional output node. 
   
   
     14. The device of  claim 12 , wherein the at least first and second pre-drivers are additionally responsive to a control input signal, the control input signal determining whether the at least first and second pre-drivers are operating in the slew mode or the non-slew mode. 
   
   
     15. The device of  claim 10 , wherein a fixed active signal is applied to the second input node of the first pre-driver. 
   
   
     16. The device of  claim 10 , further comprising:
 at least two second-polarity output transistors, each output transistor having a control terminal and two output terminals, wherein the output terminals of the at least two second-polarity output transistors are coupled in parallel between a second node and the output node, the second node adapted to couple to a second power source; and 
 at least third and fourth pre-drivers, each pre-driver having at least first and second input nodes and at least first and second output nodes, each first output nodes coupling to a corresponding one of the control terminals of the two second-polarity output transistors; 
 wherein the second input node of the fourth pre-driver is coupled to the second output node of the third pre-driver, and the first input node of the least third and fourth pre-drivers being driven by a second input signal, and 
 wherein the third and fourth pre-drivers are each adapted to be programmably configured to operate in:
 a non-slew node in which an output signal is asserted on the first output node in response to the second input signal being asserted; and 
 a slew mode in which, in response to the second input signal on the first input node and an input signal on the second input node being concurrently asserted, an output signal is asserted on the first output node and an output signal is asserted the second output node, the assertion of the output signal on the second output node being delayed with respect to the assertion of the output signal on the first output node. 
 
 
   
   
     17. A method of operating an output buffer, comprising the steps of:
 sequentially sourcing a plurality of currents to an output node in response to a first signal being asserted; and 
 terminating the sourcing of the plurality of currents to the output node substantially simultaneously upon negation of the first signal, wherein the output buffer supports;
 a slew mode in which the sourcing of the plurality of currents to the output node occurs sequentially; and 
 a non-slew mode in which the sourcing of the plurality of currents to the output node occurs substantially simultaneously. 
 
 
   
   
     18. The method of  claim 17 , further comprising the steps of:
 sequentially sinking a plurality of currents from the output node in response to a second signal being asserted; and 
 terminating the sinking of the plurality of currents from the output node substantially simultaneously upon negation of the second signal; 
 wherein the step of sequentially sinking the plurality of currents from the output node occurs after the step of terminating the sourcing of the plurality of currents to the output node.