Inventor · disambiguated record
John Schadt
Also filed as: SCHADT JOHN · SCHADT JOHN A · SCHADT JOHN ANTHONY
34 granted patents·482 citations·filing 1999–2019
97Inventor score
Top patents by PatentIndex Score
34 records- 0194US6404226B1Integrated circuit with standard cell logic and spare gatesLATTICE SEMICONDUCTOR CORP·Filed 1999·Granted Jun 11, 2002·128 cites·29 claims
- 0292US8248136B1Low-power, glitch-less, configurable delay elementZHANG FULONG·Filed 2011·Granted Aug 21, 2012·15 cites·20 claims
- 0391US6975137B1Programmable logic devices with integrated standard-cell logic blocksLATTICE SEMICONDUCTOR CORP·Filed 2005·Granted Dec 13, 2005·20 cites·18 claims
- 0490US7605609B1Programmable level shifterLATTICE SEMICONDUCTOR CORP·Filed 2007·Granted Oct 20, 2009·19 cites·16 claims
- 0590US7573770B1Distributed front-end FIFO for source-synchronized interfaces with non-continuous clocksLATTICE SEMICONDUCTOR CORP·Filed 2007·Granted Aug 11, 2009·22 cites·20 claims
- 0690US7495467B2Temperature-independent, linear on-chip termination resistanceLATTICE SEMICONDUCTOR CORP·Filed 2005·Granted Feb 24, 2009·16 cites·19 claims
- 0789US8324934B1Programmable bufferTRUONG KEITH·Filed 2011·Granted Dec 4, 2012·27 cites·21 claims
- 0889US6870395B2Programmable logic devices with integrated standard-cell logic blocksLATTICE SEMICONDUCTOR CORP·Filed 2003·Granted Mar 22, 2005·36 cites·27 claims
- 0987US7129749B1Programmable logic device having a configurable DRAM with transparent refreshLATTICE SEMICONDUCTOR CORP·Filed 2004·Granted Oct 31, 2006·34 cites·19 claims
- 1084US8461894B1Low-power configurable delay elementZHANG FULONG·Filed 2012·Granted Jun 11, 2013·6 cites·15 claims
- 1183US8912933B1Serializer with multiple stagesZHANG FULONG·Filed 2012·Granted Dec 16, 2014·7 cites·20 claims
- 1283US7009433B2Digitally controlled delay cellsLATTICE SEMICONDUCTOR CORP·Filed 2003·Granted Mar 7, 2006·35 cites·18 claims
- 1382US7262630B1Programmable termination for single-ended and differential schemesLATTICE SEMICONDUCTOR CORP·Filed 2005·Granted Aug 28, 2007·11 cites·30 claims
- 1481US10819318B1Single event upset immune flip-flop utilizing a small-area highly resistive elementMICROCHIP TECH INC·Filed 2019·Granted Oct 27, 2020·4 cites·14 claims
- 1581US6600341B2Integrated circuit and associated design method using spare gate islandsLATTICE SEMICONDUCTOR CORP·Filed 2002·Granted Jul 29, 2003·30 cites·18 claims
- 1676US7547995B1Dynamic over-voltage protection scheme for interface circuitryLATTICE SEMICONDUCTOR CORP·Filed 2006·Granted Jun 16, 2009·8 cites·9 claims
- 1772US8274412B1Serializer with odd gearing ratioZHANG FULONG·Filed 2011·Granted Sep 25, 2012·4 cites·20 claims
- 1870US7586325B1Integrated circuit having independent voltage and process/temperature controlLATTICE SEMICONDUCTOR CORP·Filed 2007·Granted Sep 8, 2009·6 cites·12 claims
- 1969US6822477B1Integrated circuit and associated design method using spare gate islandsLATTICE SEMICONDUCTOR CORP·Filed 2003·Granted Nov 23, 2004·14 cites·20 claims
- 2065US7183798B1Synchronous memoryLATTICE SEMICONDUCTOR CORP·Filed 2005·Granted Feb 27, 2007·5 cites·20 claims
- 2164US7808855B1Distributed front-end FIFO for source-synchronous interfaces with non-continuous clocksLATTICE SEMICONDUCTOR CORP·Filed 2009·Granted Oct 5, 2010·2 cites·13 claims
- 2260US7505752B1Receiver for differential and reference-voltage signaling with programmable common modeLATTICE SEMICONDUCTOR CORP·Filed 2005·Granted Mar 17, 2009·1 cites·19 claims
- 2360US6814296B2Integrated circuit and associated design method with antenna error control using spare gatesLATTICE SEMICONDUCTOR CORP·Filed 2002·Granted Nov 9, 2004·8 cites·16 claims
- 2457US7215149B1Interface circuitry for electrical systemsLATTICE SEMICONDUCTOR CORP·Filed 2004·Granted May 8, 2007·7 cites·30 claims
- 2555US7844243B1Receiver for differential and reference voltage signaling with programmable common modeLATTICE SEMICONDUCTOR CORP·Filed 2009·Granted Nov 30, 2010·0 cites·4 claims
- 2654US7187203B1Cascadable memoryLATTICE SEMICONDUCTOR CORP·Filed 2004·Granted Mar 6, 2007·6 cites·22 claims
- 2753US7616029B1Hysteresis-based processing for applications such as signal bias monitorsLATTICE SEMICONDUCTOR CORP·Filed 2007·Granted Nov 10, 2009·2 cites·10 claims
- 2852US7714608B1Temperature-independent, linear on-chip termination resistanceLATTICE SEMICONDUCTOR CORP·Filed 2009·Granted May 11, 2010·0 cites·15 claims
- 2949US6781170B2Integrated circuit base transistor structure and associated programmable cell libraryLATTICE SEMICONDUCTOR CORP·Filed 2002·Granted Aug 24, 2004·6 cites·19 claims
- 3047US6877667B1Integrated circuit and associated design method with antenna error control using spare gatesLATTICE SEMICONDUCTOR CORP·Filed 2003·Granted Apr 12, 2005·1 cites·20 claims
- 3140US6943582B1Programmable I/O structure for FPGAs and the like having shared circuitryLATTICE SEMICONDUCTOR CORP·Filed 2003·Granted Sep 13, 2005·1 cites·34 claims
- 3240US6940779B2Programmable broadcast initialization of memory blocksLATTICE SEMICONDUCTOR CORP·Filed 2003·Granted Sep 6, 2005·1 cites·32 claims
- 3339US7443192B1Output buffer with digital slew controlLATTICE SEMICONDUCTOR CORP·Filed 2006·Granted Oct 28, 2008·0 cites·18 claims
- 3431US8539409B1Simultaneous development of complementary IC familiesMURRAY SHAWN·Filed 2011·Granted Sep 17, 2013·0 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →