Inventor

DONG YINGDA

US245 patents

⚠️ This page may combine multiple inventors who share the name “DONG YINGDA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DONG YINGDA

SANDISK TECHNOLOGIES INC

Reducing hot electron injection type of read disturb in 3D non-volatile memory for edge word lines

Selective removal of charge-trapping layer for select gate transistors and dummy memory cells in 3D stacked memory

Method of reducing hot electron injection type of read disturb in dummy memory cells

Three dimensional NAND device with channel contacting conductive source line and method of making thereof

Reducing hot electron injection type of read disturb in 3D non-volatile memory

Three-dimensional memory structure having a back gate electrode

NAND boosting using dynamic ramping of word line voltages

Word line dependent channel pre-charge for memory

Three-dimensional memory structure having self-aligned drain regions and methods of making thereof

Method of reducing hot electron injection type of read disturb in memory

Data recovery in a 3D memory device with a short circuit between word lines

Reduced erase-verify voltage for first-programmed word line in a memory device

Balancing programming speeds of memory cells in a 3D stacked memory

Adaptive increase in control gate voltage of a dummy memory cell to compensate for inadvertent programming

Controlling pass voltages to minimize program disturb in charge-trapping memory

Charge redistribution during erase in charge trapping memory

Temperature dependent voltage to unselected drain side select transistor during program of 3D NAND

Dynamic erase voltage step size selection for 3D non-volatile memory

Dynamically adjustable erase and program levels for non-volatile memory

Three-dimensional non-volatile memory device having a silicide source line and method of making thereof

Three-dimensional memory devices having a single layer channel and methods of making thereof

Selective removal of charge-trapping layer for select gate transistor and dummy memory cells in 3D stacked memory

Word line-dependent ramping of pass voltage and program voltage for three-dimensional memory

Method of reducing hot electron injection type of read disturb in dummy memory cells

Programming memory with reduced short-term charge loss

Reducing weak-erase type read disturb in 3D non-volatile memory

SANDISK TECHNOLOGIES LLC

Memory hole size variation in a 3D stacked memory

Reducing read disturb in two-tier memory device by modifying ramp up rate of word line voltages during channel discharge

Three-dimensional memory device including partially surrounding select gates and fringe field assisted programming thereof

Reducing disturbs with delayed ramp up of selected word line voltage after pre-charge during programming

Forming memory cell film in stack opening

Programming of dummy memory cell to reduce charge loss in select gate transistor

Grouping memory cells into sub-blocks for program speed uniformity

Reducing select gate injection disturb at the beginning of an erase operation

Dummy word line bias ramp rate during programming

Data recovery method after word line-to-word line short circuit

Non-volatile memory with customized control of injection type of disturb during read operations

Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof

Dynamic tuning of first read countermeasures

Mitigating hot electron program disturb

Word line ramping down scheme to purge residual electrons

Reducing disturbs with delayed ramp up of dummy word line after pre-charge during programming

Doping channels of edge cells to provide uniform programming speed and reduce read disturb

Temperature dependent erase in non-volatile storage

SANDISK CORP

Read operation for memory with compensation for coupling based on write-erase cycles

Non-volatile memory using multiple boosting modes for reduced program disturb

Data pattern sensitivity compensation using different voltage

Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data

System for performing data pattern sensitivity compensation using different voltage

DONG YINGDA

Reducing weak-erase type read disturb in 3D non-volatile memory