Inventor

TOLL BRET

US60 patents

⚠️ This page may combine multiple inventors who share the name “TOLL BRET”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TOLL BRET

INTEL CORP

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems and methods for performing matrix compress and decompress instructions

Method and apparatus for disabling a clock signal within a multithreaded processor

Method and apparatus for disabling a clock signal within a multithreaded processor

Systems for performing instructions for fast element unpacking into 2-dimensional registers

Method and apparatus for performing multiply-add operations on packed byte data

Systems and methods to load a tile register pair

Systems and methods to zero a tile register pair

Systems and methods for performing instructions specifying ternary tile logic operations

Systems and methods for performing instructions to transform matrices into row-interleaved format

Systems and methods for performing instructions to transpose rectangular tiles

Systems and methods for implementing chained tile operations

Multiple register memory access instructions, processors, methods, and systems

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems, methods, and apparatuses for matrix operations

Systems and methods to store a tile register pair to memory

Systems and methods for computing dot products of nibbles in two tile operands

Systems and methods for performing matrix compress and decompress instructions

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems, methods, and apparatuses for dot product operations

Systems and methods to load a tile register pair

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems and methods for performing horizontal tile operations

Systems for performing instructions for fast element unpacking into 2-dimensional registers

Systems and methods for implementing chained tile operations

Systems and methods for performing instructions to transpose rectangular tiles

Systems and methods for performing duplicate detection instructions on 2D data

Systems and methods for performing matrix compress and decompress instructions

Systems and methods to zero a tile register pair

Apparatus and method for processing structure of arrays (SoA) and array of structures (AoS) data

Multiple register memory access instructions, processors, methods, and systems

Multiple register memory access instructions, processors, methods, and systems

Multiple register memory access instructions, processors, methods, and systems

Multiple register memory access instructions, processors, methods, and systems

Multiple register memory access instructions, processors, methods, and systems

Multiple register memory access instructions, processors, methods, and systems

Multiple register memory access instructions, processors, methods, and systems

Systems and methods for performing matrix compress and decompress instructions

Virtualization and multi-tenancy support in graphics processors

Systems, apparatuses, and methods for controllable sine and/or cosine operations

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems and methods to store a tile register pair to memory

Systems, methods, and apparatuses for matrix operations

Systems for performing instructions to quickly convert and use tiles as 1D vectors

Systems and methods to load a tile register pair

Systems and methods for computing dot products of nibbles in two tile operands

VALENTINE ROBERT

Compressed instruction format

Compressed instruction format

ERMOLAEV IGOR

Systems, apparatuses, and methods for performing a shuffle and operation (shuffle-op)

CORBAL SAN ADRIAN JESUS

Floating point rounding processors, methods, systems, and instructions