Inventor

ABEDIFARD EBRAHIM

US129 patents

⚠️ This page may combine multiple inventors who share the name “ABEDIFARD EBRAHIM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ABEDIFARD EBRAHIM

MICRON TECHNOLOGY INC

Memory block erasing in a flash memory device

Address decoding in multiple-bank memory architectures

Memory block erasing in a flash memory device

Preconditioning global bitlines

Memory with row redundancy

Flash cell with trench source-line connection

Methods of accessing floating-gate memory cells having underlying source-line connections

Memory with row redundancy

Write and erase protection in a synchronous memory

Methods of operating a multiple bit line column redundancy scheme having primary and redundant local and global bit lines

Multiple bit line column redundancy with primary local and global bit lines and redundant local and global bit lines

Redundancy selection in memory devices with concurrent read and write

Multiple bit line column redundancy

Memory device redundancy selection having test inputs

Array organization for high-performance memory devices

Current limiting negative switch circuit

Clock generation circuits and methods

Method and apparatus for programming flash memory

Method and apparatus for discharging an array well in a flash memory device

Sensing for memory read and program verify operations in a non-volatile memory device

NAND memory device and programming methods

Method and apparatus for programming row redundancy fuses so decoding matches internal pattern of a memory array

NAND interface

Non-volatile one time programmable memory

Methods of forming memory cells and arrays having underlying source-line connections

Common wordline flash array architecture

Method and apparatus using parasitic capacitance for synchronizing signals a device

Flash cell with trench source-line connection

Write and erase protection in a synchronous memory

Array organization for high-performance memory devices

Lead-over-chip leadframes

Memory device testing

Clock generation circuits

Architecture, package orientation and assembly of memory devices

AVALANCHE TECHNOLOGY INC

Fast programming of magnetic random access memory (MRAM)

Magnetic memory emulating dynamic random access memory (DRAM)

Method for reading and writing multi-level cells

Pulse programming techniques for voltage-controlled magnetoresistive tunnel junction (MTJ)

MRAM with sidewall protection and method of fabrication

Method and apparatus for reading a magnetic tunnel junction using a sequence of short pulses

Method and apparatus for programming a magnetic tunnel junction (MTJ)

Magnetic memory read circuit and calibration method therefor

Programming of magnetic random access memory (MRAM) by boosting gate voltage

SATOH KIMIHIRO

Redeposition control in MRAM fabrication process

MRAM fabrication method with sidewall cleaning

MRAM with sidewall protection and method of fabrication

MRAM with sidewall protection and method of fabrication

ABEDIFARD EBRAHIM

NAND interface

Method and apparatus for increasing the reliability of an access transitor coupled to a magnetic tunnel junction (MTJ)

Shared transistor in a spin-torque transfer magnetic random access memory (STTMRAM) cell