Sensing for memory read and program verify operations in a non-volatile memory device

Abstract

Methods for sensing in a memory device, a memory device, and a memory system are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cell. A ramped voltage turns on the selected memory cell when the ramped voltage reaches the threshold voltage to which the selected memory cell is programmed. In one embodiment, the turned on memory cell discharges its respective bit line.

1. A method for sensing in a memory device, the method comprising:
 precharging unselected memory cells to a pass voltage; 
 precharging at least one data line to a first voltage level; 
 grounding a source line; and 
 applying a ramped voltage to at least one selected memory cell that turns on the at least one selected memory cell when the ramped voltage increases to a voltage level substantially equal to a threshold voltage of the at least one selected memory cell, wherein the turned on memory cell discharges the at least one data line that is coupled to the turned on memory cell. 
 
     
     
       2. The method of  claim 1  and further including generating at least one read pulse after the sensing to read a voltage level. 
     
     
       3. The method of  claim 1  wherein precharging comprises precharging an access line coupled to control gates of the unselected memory cells. 
     
     
       4. The method of  claim 2  wherein the at least one read pulse comprises a different read pulse for each voltage level being read. 
     
     
       5. The method of  claim 2  and further including comparing each read voltage level to a reference voltage level. 
     
     
       6. The method of  claim 1  and further including generating at least one read pulse during the sensing to read a voltage level. 
     
     
       7. The method of  claim 1  wherein different read pulses are generated at different times while applying the ramped voltage. 
     
     
       8. The method of  claim 1  wherein the ramped voltage has a minimum voltage of 0V and a maximum voltage of 3.5V. 
     
     
       9. The method of  claim 1  wherein the at least one data line is discharged from the first voltage level to a second voltage level that is indicative of the threshold voltage. 
     
     
       10. The method of  claim 1  wherein the pass voltage is between 4.5V and 6.0V. 
     
     
       11. A method for sensing in a non-volatile memory device, the method comprising:
 precharging unselected memory cells to a pass voltage; 
 grounding a source line; 
 precharging a plurality of data lines to a first voltage level; 
 turning on select gate transistors, each of which couples a respective one of a plurality of selected memory cells to a different data line; and 
 applying a ramped voltage to the plurality of selected memory cells that turns on a respective one of the selected memory cell when the ramped voltage increases to a threshold voltage for that respective one of the selected memory cells wherein a turned on memory cell discharges the data line coupled to the turned on memory cell to a second voltage level that is indicative of the threshold voltage. 
 
     
     
       12. The method of  claim 11  wherein the pass voltage is at a level that permits a maximum threshold voltage to pass. 
     
     
       13. The method of  claim 11  and further including comparing the second voltage level of each data line to a reference threshold voltage level to determine a state of the turned on memory cell. 
     
     
       14. A method for sensing in a non-volatile memory device, the method comprising:
 precharging unselected memory cells to a pass voltage that allows a maximum threshold voltage to pass; 
 precharging a source line to a voltage level; 
 turning on a select gate drain transistor that couples a respective one of a plurality of selected memory cells to a different data line; and 
 applying a ramped voltage to the plurality of selected memory cells that turns on each selected memory cell when the ramped voltage reaches a threshold voltage to which each selected memory cell is programmed, wherein a turned on memory cell charges its respective data line to a voltage indicative of the threshold voltage to which the selected memory cell is programmed. 
 
     
     
       15. The method of  claim 14  wherein the select gate drain transistor is turned off after the sensing. 
     
     
       16. The method of  claim 14  wherein the select gate drain transistor is turned off when the voltages on the data lines are stable. 
     
     
       17. The method of  claim 14  and further including generating a plurality of read pulses during the sensing wherein each read pulse enables sense circuitry to sense the voltage indicative of the threshold voltage. 
     
     
       18. The method of  claim 17  and further including the sense circuitry performing a plurality of compare operations between each sensed voltage indicative of the threshold voltage and at least one reference voltage. 
     
     
       19. The method of  claim 14  and further including generating a plurality of read pulses after the sensing wherein each read pulse enables sense circuitry to sense the voltage indicative of the threshold voltage. 
     
     
       20. The method of  claim 19  wherein each read pulse is comprised of a different voltage amplitude. 
     
     
       21. The method of  claim 20  wherein each successive read pulse has a greater voltage amplitude than a previous read pulse. 
     
     
       22. A non-volatile memory device comprising:
 a memory array comprising a plurality of memory cells coupled to word lines and bit lines, the memory array further comprising a source line; and 
 memory control circuitry coupled to the memory array and configured to control a sensing operation that precharges unselected word lines, grounds the source line, turns on select gate transistors, and controls the generation of a ramped voltage coupled to a selected word line wherein each selected memory cell coupled to the selected word line are turned on when the ramped voltage increases to a threshold voltage for each selected memory cell such that each turned on memory cell discharges a bit line to which it is coupled. 
 
     
     
       23. The non-volatile memory device of  claim 22  wherein the device is a NAND flash memory device and the plurality of memory cells are floating gate memory cells. 
     
     
       24. A memory system comprising:
 a controller for generating memory control signals; and 
 a non-volatile memory device coupled to the controller and operating in response to the memory control signals, the memory device comprising:
 a memory array comprising a plurality of memory cells coupled to a source line; and 
 memory control circuitry coupled to the memory array for controlling operation of the memory array in response to the memory control signals, wherein the control circuitry is configured to control a sensing operation that precharges unselected memory cells, precharges the source line, turns on a select gate drain transistor to enable selected memory cell access to a data line, and controls a ramped voltage coupled to selected memory cells that turn on when the ramped voltage reaches a threshold voltage to which the selected memory cell is programmed such that the turned on memory cell charges its respective data line. 
 
 
     
     
       25. The non-volatile memory device of  claim 24  wherein the plurality of memory cells are coupled to word lines in rows and bit lines in columns wherein the columns of memory cells are comprised of a NAND series string of memory cells. 
     
     
       26. The non-volatile memory device of  claim 24  wherein the memory control signals comprise program and erase control signals. 
     
     
       27. A method for sensing in a memory device, the method comprising:
 precharging unselected memory cells to a pass voltage; 
 grounding at least one data line; 
 precharging a source line to a voltage level; and 
 applying a ramp voltage to at least one selected memory cell that turns on the at least one selected memory cell when the ramped voltage increases to a voltage level substantially equal to a threshold voltage of the at least one selected memory cell, wherein the turned on memory cell charges the at least one data line that is coupled to the turned on memory cell. 
 
     
     
       28. The method of  claim 27  wherein the pass voltage is at least 4V greater than the source line voltage level. 
     
     
       29. A non-volatile memory device comprising:
 a memory array comprising a plurality of memory cells coupled to word lines and bit lines, the memory array further comprising a source line; and 
 memory control circuitry coupled to the memory array and configured to control a sensing operation that precharges unselected word lines, grounds the source line, turns on select gate transistors, and controls the generation of a ramped voltage coupled to a selected word line wherein each selected memory cell coupled to the selected word line are turned on when the ramped voltage increases to a threshold voltage for each selected memory cell such that each turned on memory cell charges a bit line to which it is coupled. 
 
     
     
       30. The memory device of  claim 29  and further comprising a read circuit coupled between each bit line and a sense amplifier circuit. 
     
     
       31. The memory device of  claim 30  wherein the read circuit is comprised of a bit line control transistor and a boost signal circuit that increases an amplitude of a signal from the bit line.