Inventor

MANDELMAN JACK ALLAN

US120 patents

⚠️ This page may combine multiple inventors who share the name “MANDELMAN JACK ALLAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MANDELMAN JACK ALLAN

IBM

Semiconductor structures integrating damascene-body FinFET&#39;s and planar devices on a common substrate and methods for forming such semiconductor structures

Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure

Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation

Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure

Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates

Methods for forming semiconductor structures with buried isolation collars and semiconductor structures formed by these methods

Fin PIN diode

Bulk FinFET device

Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation

Transistor having substantially isolated body and method of making the same

Trench storage dram cell including a step transfer device

Vertical double-gate field effect transistor

Vertical double-gate field effect transistor

Switched body SOI (silicon on insulator) circuits and fabrication method therefor

Pillar transistor incorporating a body contact

Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering

Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby

Methods for fabricating a semiconductor structure using a mandrel and semiconductor structures formed thereby

Reduced-resistance finFETs by sidewall silicidation and methods of manufacturing the same

Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures

Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures

Self-aligned, planarized thin-film transistors, devices employing the same

Method of making low voltage active body semiconductor device

Semiconductor integrated circuits with mesas

Methods of making a trench storage DRAM cell including a step transfer device

DRAM cell with transfer device extending along perimeter of trench storage capacitor

Low voltage active body semiconductor device

Trench isolated FET devices, and method for their manufacture

Semiconductor structures integrating damascene-body FinFET&#39;s and planar devices on a common substrate and methods for forming such semiconductor structures

Bulk FinFET device

Semiconductor device structures incorporating voids and methods of fabricating such structures

Semiconductor structures integrating damascene-body FinFET&#39;s and planar devices on a common substrate and methods for forming such semiconductor structures

Bulk FinFET device

Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same

High performance logic and high density embedded dram with borderless contact and antispacer

Method and structure for salicide trench capacitor plate electrode

Method of forming self-limiting polysilicon LOCOS for DRAM cell

Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate

Threshold voltage tailoring of corner of MOSFET device

Threshold voltage tailoring of the corner of a MOSFET device

Deep trench cell capacitor with inverting counter electrode

Optical FET

Wire shape conferring reduced crosstalk and formation methods

Intrinsic dual gate oxide MOSFET using a damascene gate process

Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures

Method of making contacted body silicon-on-insulator field effect transistor

Pillar transistor incorporating a body contact

Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures

Fuse/anti-fuse structure and methods of making and programming same

SIEMENS AG

Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETS

Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures

Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures

Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures