Inventor

NOWKA KEVIN J

US34 patents

⚠️ This page may combine multiple inventors who share the name “NOWKA KEVIN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NOWKA KEVIN J

IBM

Pre-reduction technique within a multiplier/accumulator architecture

Dynamically scalable low voltage clock generation system

Dynamic leakage control circuit

Low gate-leakage virtual rail circuit

System and method for reducing latency in a dynamic circuit

Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance

Power-gating cell for virtual power rail control

Multi-mode VCO

Low power low voltage transistor—transistor logic I/O driver

Method and apparatus for performing rotate operations using cascaded multiplexers

Method and apparatus for testing pipelined dynamic logic

Body-contacted and double gate-contacted differential logic circuit and method of operation

Glitch-less clock selector

Clock divider with bypass and stop clock

Optimizing SRAM performance over extended voltage or process range using self-timed calibration of local clock generator

Storage array including a local clock buffer with programmable timing

Pulsed ring oscillator circuit for storage cell read timing evaluation

Pulsed ring oscillator circuit for storage cell read timing evaluation

Dual-gate dynamic logic circuit with pre-charge keeper

Controlled load limited switch dynamic logic circuitry

Interface circuit for coupling between logic circuit domains

Dual mode charge pump

Method and apparatus for reducing leakage in dynamic silicon-on-insulator logic circuits

Method for evaluating memory cell performance

Buffer/driver circuits

Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance

Technique for mitigating gate leakage during a sleep state

Digital circuit with dynamic power and performance control via per-block selectable operating voltage

Circuit for controlling leakage

Static pulsed bus circuit and method having dynamic power supply rail selection

CHANG LELAND

Test structure for characterizing multi-port static random access memory and register file arrays

Test structure for characterizing multi-port static random access memory and register file arrays

INTERNATIIONAL BUSINESS MACHIN

Self limiting gate leakage driver

CHEN LEI

System and method for implementing simplified arithmetic logic unit processing of value-based control dependence sequences