Body-contacted and double gate-contacted differential logic circuit and method of operation

Abstract

A differential logic circuit ( 20, 120, 220, 320, 420 and 520 ) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure ( 22, 122, 222, 322, 422 ) that is connected to evaluate transistors ( 50, 52, 54, 56 ). In several embodiments, the outputs of the load transistors ( 30, 32 ) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers ( 160, 178 ) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.

What is claimed is:  
     
       1. A logic circuit comprising: 
       plurality of evaluate transistors, each leaving a body; and  
       a differential load structure connected to each of said bodies;  
       wherein said differential load structure includes first and second transistors, each having an input and an output, further wherein said plurality of evaluate transistors includes a plurality of transistors in a first evaluate tree, each having an input, and a plurality of transistors in a second evaluate tree, each having an input, the logic circuit tither including a first level-shifting output buffer connected between said output of said first transistor and said input of a transistor in said first evaluate tree and a second level-shifting output buffer connected between said output of said second transistor and said input of a transistor in said second evaluate tree.  
     
     
       2. A logic circuit according to  claim 1 , wherein the logic circuit further includes a precharge clock for providing a precharge clock signal, said precharge clock connected to said first and second transistors. 
     
     
       3. A logic circuit according to  claim 1 , wherein transistors in said first evaluate tree are connected in series and transistors in said second evaluate tree are connected in parallel. 
     
     
       4. A logic circuit according to  claim 1 , wherein said plurality of evaluate transistors and said first and second transistors are silicon-on-insulator transistors. 
     
     
       5. A logic circuit according to  claim 1 , wherein said level-shifting output buffer includes a plurality of transistors that reduce V DD  by at least one V T . 
     
     
       6. A method of enhancing stability of a differential logic circuit, comprising the steps of: 
       providing a differential logic circuit having a plurality of transistors arranged in a first evaluate tree and a second evaluate tree, each transistor having one of a single gate with a body and double gate, and  
       a differential load structure having a first intermediate output node and a second intermediate output node; and  
       biasing, in said first evaluate tree, said body of said each transistor when said each transistor has a single gate and said at least one of said double gates of said each transistor when said each transistor has a double gate with voltage present at said second intermediate node, and biasing, in said second evaluate tree, said body of said each transistor when said each transistor has a single gate and said at least one of said double gates of said each transistor when said each transistor has a double gate with voltage present at said first intermediate node.  
     
     
       7. A method according to  claim 6 , wherein said biasing step involves biasing said bodies and said at least one of said double gates with a voltage V DD −V T . 
     
     
       8. A method according to  claim 6 , wherein said biasing step involves biasing said bodies and said at least one of said double gates with a voltage V DD . 
     
     
       9. A method according to  claim 6 , further including the step of biasing signals at said first and second intermediate nodes so as to provide first and second logical outputs that are at V DD −V T . 
     
     
       10. A method according to  claim 6 , further including the step of biasing signals at said first and second intermediate nodes so as to provide first and second logical outputs that are at V DD . 
     
     
       11. A logic circuit, comprising: 
       a plurality of evaluate transistors, each laving first and second gates; and  
       a differential load structure connected to said first gates of said plurality of transistors;  
       wherein said plurality of evaluate transistors includes a plurality of transistors in a first evaluate tree for receiving a logical input and a plurality of transistors in a second evaluate tree for receiving a complement of said logical input; and said differential load structure includes first and second transistors, each providing an output, wherein said output of said first transistor is connected to said first gates of said transistors in said second evaluate tree and said output of said second transistor is connected to said first gates of said transistors in said first evaluate tree.  
     
     
       12. A logic circuit according to  claim 11 , wherein the logic circuit further includes a precharge clock connected to said first and second transistors for providing a precharge clock signal to said first and second transistors. 
     
     
       13. A logic circuit according to  claim 4 , wherein: 
       said first and second transistors each have first and second gates; and  
       said output of said first transistor is connected to said first gate of said second transistor and said output of said second transistor is connected to said first gate said first transistor.  
     
     
       14. A logic circuit according to  claim 11 , wherein said plurality of evaluate transistors are NFETs and said differential circuit includes a plurality of PFET transistors. 
     
     
       15. A logic circuit according to  claim 14 , wherein said NFET and PFET transistors are silicon-on-insulator transistors. 
     
     
       16. A logic circuit according to  claim 11 , wherein transistors in said first evaluate tree are connected in series and transistors in said second evaluate tree are connected in parallel. 
     
     
       17. A logic circuit according to  claim 11 , wherein said plurality of evaluate transistors and said first and second transistors are silicon-on-insulator transistors. 
     
     
       18. A method of enhancing stability of a differential logic circuit, comprising the steps of: 
       providing a differential logic circuit having a plurality of transistors arranged in a first evaluate tree and a second evaluate tree, each transistor having a double gate, and a differential load structure having a first intermediate output node and a second intermediate output node; and  
       biasing, in said first evaluate tree, at least one of said double gates of said each transistor with voltage present at said second intermediate node, and biasing, in said second evaluate tree, at least one of said double gates of said each transistor with voltage present at said first intermediate node.  
     
     
       19. A method according to  claim 18 , wherein said biasing step involves biasing at least one of said double gates with a voltage V DD −V T . 
     
     
       20. A method according to  claim 18 , wherein said biasing step involves biasing at least one of said double gates with a voltage V DD . 
     
     
       21. A method according to  claim 18 , further including the step of biasing signals at said first and second intermediate nodes so as to provide first and second logical outputs that are at V DD −v T . 
     
     
       22. A method according to  claim 18 , further including the step of biasing signals at first and second intermediate nodes so as to provide first and second logical outputs that are V DD .