Inventor

KOSONOCKY STEPHEN V

US66 patents

⚠️ This page may combine multiple inventors who share the name “KOSONOCKY STEPHEN V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOSONOCKY STEPHEN V

IBM

Intelligent media memory statically mapped in unified memory architecture

Digital logic with reduced leakage

Method of dynamically controlling cache size

Data retention registers

Charge recycling power gate

Machine code builder derived power consumption reduction

Charge recycling power gate

Quasi-static random access memory

Loadless NMOS four transistor dynamic dual Vt SRAM cell

Non-abrupt switching of sleep transistor of power gate structure

Decode path gated low active power SRAM

Method and structure for reducing gate leakage and threshold voltage fluctuation in memory cells

Self-timed read and write assist and restore circuit

Body-contacted and double gate-contacted differential logic circuit and method of operation

High performance semiconductor memory device with low power consumption

Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation

Self-regulating voltage divider for series-stacked voltage rails

Static random access memory (SRAM) cells

Memory circuits with reduced leakage power and design structures for same

Low power circuits with small voltage swing transmission, voltage regeneration, and wide bandwidth architecture

Circuits and methods for providing low voltage, high performance register files

Register file cell with soft error detection and circuits and methods using the cell

Performance increase technique for use in a register file having dynamically boosted wordlines

Detector for alpha particle or cosmic ray

Methods for incorporating high dielectric materials for enhanced SRAM operation and structures produced thereby

Static random access memory cell with improved stability

Low power circuits with small voltage swing transmission, voltage regeneration and wide bandwidth architecture

Dynamic adder with reduced logic

Methods and apparatus for employing feedback body control in cross-coupled inverters

Three-dimensional cascaded power distribution in a semiconductor device

Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits

SRAM cell with bootstrapped power line

ADVANCED MICRO DEVICES INC

Master/slave frequency locked loop

Sampling circuit with reduced metastability exposure

Fault detection for a distributed signal line

Dynamic reliability quality monitoring

On die voltage regulation with distributed switches

On-demand IP initialization within power states

Device and method for two-stage transitioning between reduced power states

Method and apparatus for managing power states

Device and method for efficient transitioning to and from reduced power state

Using a hardware-based controller for power state management

Device and method for efficient transitioning to and from reduced power state

Hierarchical state save and restore for device with varying power states

KOSONOCKY STEPHEN V

Electrostatic discharge circuit

Power supply monitor

Ring power gating with distributed currents using non-linear contact placements

Interposer including voltage regulator and method therefor

BHAVNAGARWALA AZEEZ

Circuits and methods for characterizing random variations in device characteristics in semiconductor integrated circuits

ATI TECHNOLOGIES ULC

Adaptive oscillator for clock generation