Inventor

BERNSTEIN KERRY

US143 patents

⚠️ This page may combine multiple inventors who share the name “BERNSTEIN KERRY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BERNSTEIN KERRY

IBM

CMOS back-gated keeper technique

3-dimensional integrated circuit architecture, structure and method for fabrication thereof

Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement

FinFET transistor and circuit

DTCMOS circuit having improved speed

Integrated high-performance decoupling capacitor and heat sink

Dual wired integrated circuit chips

FinFETs with long gate length at high density

Intralevel decoupling capacitor, method of manufacture and testing circuit of the same

Intralevel decoupling capacitor, method of manufacture and testing circuit of the same

Damascene metal capacitor

Multicore processor having storage for core-specific operational data

Silicon heat spreader mounted in-plane with a heat source and method therefor

3-dimensional integrated circuit architecture, structure and method for fabrication thereof

Method of manufacturing an intralevel decoupling capacitor

Integrated high-performance decoupling capacitor and heat sink

SOI CMOS dynamic circuits having threshold voltage control

Multi-port system

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Double-sided integrated circuit chips

Wafer level I/O test, repair and/or customization enabled by I/O layer

Double-sided integrated circuit chips

Wafer level I/O test and repair enabled by I/O layer

Methodology for fixing Qcrit at design timing impact

Apparatus for reducing soft errors in dynamic circuits

Body-contacted and double gate-contacted differential logic circuit and method of operation

Method for adding decoupling capacitance during integrated circuit design

System technique for detecting soft errors in statically coupled CMOS logic

Capacitor and method for forming same

Robust domino circuit design for high stress conditions

Voltage limiting circuit for fuse technology

SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and method for making same

Leakage compensation circuit

Self-regulating voltage divider for series-stacked voltage rails

Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement

High performance CPL double-gate latch

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Dual wired integrated circuit chips

Power connector/decoupler integrated in a heat sink

Apparatus and method for implementing matrix-based search capability in content addressable memory devices

Chip-in-slot interconnect for 3D chip stacks

BERNSTEIN KERRY

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Electro-rheological micro-channel anisotropic cooled integrated circuits and methods thereof

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly

Adaptive linesize in a cache

Three dimensional vertical E-fuse structures and methods of manufacturing the same

BARTH JR JOHN E

Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices