FinFETs with long gate length at high density

Abstract

A method of manufacturing fin-type field effect transistors (FinFETs) forms a silicon layer above a substrate, forms a mask pattern above the silicon layer using a multi-step mask formation process, patterns the silicon layer into silicon fins using the mask pattern such that the silicon fins only remain below the mask pattern, removes the mask pattern to leave the fins on the substrate, and forms gate conductors over the fins at a non-perpendicular angle to the fins.

1. A method of manufacturing fin-type field effect transistors (FinFETs), said method comprising:
 forming a silicon layer above a substrate; 
 forming a mask pattern above said silicon layer using a multi-step mask formation process, wherein said multi-step mask formation process comprises: 
 forming, above said silicon layer, a first mask pattern that has a plurality of first mask features; and 
 forming, above said silicon layer, a second mask pattern that has a plurality of second mask features, wherein said forming of said second mask pattern comprises forming said second mask pattern such that said second mask features are interleaved with said first mask features; 
 patterning said silicon layer into silicon fins using said mask pattern such that said silicon fins remain only below said mask pattern; and 
 forming gate conductors over said fins at a non-perpendicular angle to said fins. 
 
     
     
       2. The method in  claim 1 , wherein said second mask pattern is parallel to and shifted from said first mask pattern, such that said fins are parallel to each other and are evenly spaced from each other. 
     
     
       3. The method in  claim 2 , wherein said second mask pattern doubles a density of fins created during said patterning of said silicon layer, when compared to said first mask pattern alone. 
     
     
       4. The method in  claim 1 , further comprising, after forming said gate conductors, doping exposed portions of said fins to form source and drain regions in said fins. 
     
     
       5. The method in  claim 1 , further comprising forming gate oxides on said fins before forming said gate conductors. 
     
     
       6. The method in  claim 1 , wherein said substrate comprises an insulator such that said FinFETs comprise silicon-on-insulator (SOI) structures. 
     
     
       7. The method in  claim 1 , wherein said mask pattern comprises linear features. 
     
     
       8. A method of manufacturing fin-type field effect transistors (FinFETs), said method comprising:
 forming a silicon layer above a substrate; 
 forming a first mask pattern above said silicon layer; 
 forming a second mask pattern above said silicon layer, wherein said second mask pattern is interleaved with said first mask pattern; 
 patterning said silicon layer into silicon fins using said first mask pattern and said second mask pattern such that said silicon fins remain only below said first mask pattern and said second mask pattern; and 
 forming gate conductors over said fins at a non-perpendicular angle to said fins. 
 
     
     
       9. The method in  claim 8 , wherein said second mask pattern is parallel to and shifted from said first mask pattern, such that said fins are parallel to each other and are evenly spaced from each other. 
     
     
       10. The method in  claim 8 , wherein said forming of said second mask pattern doubles a density of fins created during said patterning of said silicon layer, when compared to said first mask pattern alone. 
     
     
       11. The method in  claim 8 , further comprising, after forming said gate conductors, doping exposed portions of said fins to form source and drain regions in said fins. 
     
     
       12. The method in  claim 8 , further comprising forming gate oxides on said fins before forming said gate conductors. 
     
     
       13. The method in  claim 8 , wherein said substrate comprises an insulator such that said FinFETs comprise silicon-on-insulator (SOI) structures. 
     
     
       14. The method in  claim 8 , wherein said first mask pattern and said second mask pattern comprise linear features. 
     
     
       15. A method of manufacturing fin-type field effect transistors (FinFETs), said method comprising:
 forming a silicon layer above a substrate; 
 forming a hardmask layer above said silicon layer; 
 forming a pattern of first mandrels on said hardmask layer; 
 forming first sidewall spacers on said first mandrels; 
 removing said first mandrels to leave said first sidewall spacers on said hardmask layer; 
 forming a masking layer over said first sidewall spacers; 
 forming a pattern of second mandrels on said masking layer; 
 forming second sidewall spacers on said second mandrels; 
 removing said second mandrels to leave said second sidewall spacers on said masking layer; 
 patterning said masking layer using said second sidewall spacers as a mask, such that said masking layer remains only below said second sidewall spacers; 
 patterning said hardmask layer using said first sidewall spacers and said second sidewall spacers such that said hardmask layer remain only below said first sidewall spacers and said second sidewall spacers; 
 removing said first sidewall spacers, said second sidewall spacers, and said masking layer to leave said hardmask layer patterned on said silicon layer; 
 patterning said silicon layer into silicon fins using said hardmask layer; and 
 forming gate conductors over said fins at a non-perpendicular angle to said fins. 
 
     
     
       16. The method in  claim 15 , wherein said second mandrels are patterned parallel to and shifted from positions of said first mandrels, such that said fins are parallel to each other and are evenly spaced from each other. 
     
     
       17. The method in  claim 15 , wherein said forming of said second sidewall spacers doubles a density of fins created during said patterning of said silicon layer, when compared to said first sidewall spacers alone. 
     
     
       18. The method in  claim 15 , further comprising, after forming said gate conductors, doping exposed portions of said fins to form source and drain regions in said fins. 
     
     
       19. The method in  claim 15 , further comprising forming gate oxides on said fins before forming said gate conductors. 
     
     
       20. The method in  claim 15 , wherein said substrate comprises an insulator such that said FinFETs comprise silicon-on-insulator (SOI) structures.