P

Inventor

ARANA LEONEL

US22 patents
⚠️ This page may combine multiple inventors who share the name “ARANA LEONEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

18 patents
US7666768B2Feb 23, 2010

Through-die metal vias with a dispersed phase of graphitic structures of carbon for reduced thermal expansion and increased electrical conductance

INTEL CORP23 citations92
US7528006B2May 5, 2009

Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion

INTEL CORP17 citations83
US7892883B2Feb 22, 2011

Clipless integrated heat spreader process and materials

INTEL CORP9 citations79
US8383459B2Feb 26, 2013

Methods of processing a thermal interface material

INTEL CORP10 citations77
US7971347B2Jul 5, 2011

Method of interconnecting workpieces

INTEL CORP7 citations77
US11088103B2Aug 10, 2021

First layer interconnect first on carrier approach for EMIB patch

INTEL CORP3 citations72
US12456705B2Oct 28, 2025

First layer interconnect first on carrier approach for EMIB patch

INTEL CORP0 citations62
US12354992B2Jul 8, 2025

First layer interconnect first on carrier approach for EMIB patch

INTEL CORP0 citations62
US11948848B2Apr 2, 2024

Subtractive etch resolution implementing a functional thin metal resist

INTEL CORP0 citations62
US11817349B2Nov 14, 2023

Conductive route patterning for electronic substrates

INTEL CORP0 citations61
US12341117B2Jun 24, 2025

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates

INTEL CORP0 citations60
US11506982B2Nov 22, 2022

Prism-mask for angled patterning applications

INTEL CORP0 citations58
US12334422B2Jun 17, 2025

Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substrates

INTEL CORP0 citations55
US12027466B2Jul 2, 2024

Conductive route patterning for electronic substrates

INTEL CORP0 citations51
US12449600B2Oct 21, 2025

Position controlled waveguides and methods of manufacturing the same

INTEL CORP0 citations50
US10515824B2Dec 24, 2019

Enhanced etch anisotropy using nanoparticles as banking agents in the presence or absence of a magnetic or electrical field

INTEL CORP0 citations50
US12255130B2Mar 18, 2025

Airgap structures for high speed signal integrity

INTEL CORP0 citations48
US12033930B2Jul 9, 2024

Selectively roughened copper architectures for low insertion loss conductive features

INTEL CORP0 citations47

SWAMINATHAN RAJASEKARAN

1 patent

ARANA LEONEL

1 patent

SUPRIYA LAKSHMI

1 patent

KOSTIEW GEORGE

1 patent