Inventor

CHOI KISIK

US125 patents

⚠️ This page may combine multiple inventors who share the name “CHOI KISIK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOI KISIK

IBM

Method to improve reliability of replacement gate device

Method and structure for forming a vertical field-effect transistor using a replacement metal gate process

Method to improve reliability of replacement gate device

Replacement metal gate structure for CMOS device

Air-gap containing metal interconnects

Buried power rail at tight cell-to-cell space

Backside power rails and power distribution network for density scaling

Top via with damascene line and via

Self-aligned top via

Conductive lines with subtractive cuts

Top via stack

Well-controlled edge-to-edge spacing between adjacent interconnects

Top via interconnect having a line with a reduced bottom dimension

Top via with next level line selective growth

Gate contact over active enabled by alternative spacer scheme and claw-shaped cap

Low threshold voltage CMOS device

Enabling enhanced reliability and mobility for replacement gate planar and FinFET structures

Replacement metal gate structure for CMOS device

Quad-layer high-k for metal-insulator-metal capacitors

Full wrap around backside contact

Buried power rail directly contacting backside power delivery network

Self-aligned backside contact with deep trench last flow

Self-aligned backside contact with protruding source/drain

Trench isolation for backside contact formation

Reduced capacitance between power via bar and gates

Airgap spacer for power via

Stacked FET with extremely small cell height

Field effect transistor with backside source/drain

Buried power rail after replacement metal gate

Self-aligned buried power rail cap for semiconductor devices

SRAM with backside cross-couple

GLOBALFOUNDRIES INC

Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices

Methods of forming gate structures with multiple work functions and the resulting products

Method of forming a semiconductor device

Methods of forming replacement gate structures for transistors and the resulting devices

Methods of forming gate structures for transistor devices for CMOS applications

Semiconductor gate structure for threshold voltage modulation and method of making same

Finned semiconductor device with oxygen diffusion barrier regions, and related fabrication methods

Method for single fin cuts using selective ion implants

Gate structures for transistor devices for CMOS applications and products

Metal gate structure for midgap semiconductor device and method of making same

Replacement gate structure with low-K sidewall spacer for semiconductor devices

Methods of scaling thickness of a gate dielectric structure, methods of forming an integrated circuit, and integrated circuits

Methods of forming gate structures for CMOS based integrated circuit products and the resulting devices

Methods of forming gate structures for CMOS based integrated circuit products and the resulting devices

ANDO TAKASHI

Low threshold voltage CMOS device

Gate-last fabrication of quarter-gap MGHK FET

SEMATECH INC

Methods of modulating the work functions of film layers

KIM HOON

Integrated circuits having improved metal gate structures and methods for fabricating same

CHOI KISIK

Integrated circuit and method for fabricating the same having a replacement gate structure