Inventor

LEUNG YING-KEUNG

TW127 patents

⚠️ This page may combine multiple inventors who share the name “LEUNG YING-KEUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEUNG YING-KEUNG

TAIWAN SEMICONDUCTOR MFG CO LTD

Multi-gate device and method of fabrication thereof

Multi-gate device and method of fabrication thereof

Multi-gate device and method of fabrication thereof

FINFETs with wrap-around silicide and method forming the same

Wrap around silicide for FinFETs

Semiconductor device and manufacturing method thereof

FinFET with source/drain structure

Semiconductor structure with multi spacer

Devices including gate spacer with gap or void and methods of forming the same

Devices including gate spacer with gap or void and methods of forming the same

Devices including gate spacer with gap or void and methods of forming the same

Contacts for highly scaled transistors

Devices including gate spacer with gap or void and methods of forming the same

FinFET channel on oxide structures and related methods

Contacts for highly scaled transistors

Contacts for highly scaled transistors

Semiconductor device including a liner layer between a channel and a source/drain epitaxial layer

Stacked gate-all-around FinFET and method forming the same

FinFET device having oxide region between vertical fin structures

Contacts for highly scaled transistors

FINFETs with wrap-around silicide and method forming the same

Wrap around silicide for FinFETs

Method for manufacturing semiconductor structure with multi spacers

Input/output (I/O) devices with greater source/drain proximity than non-I/O devices

System and method for widening Fin widths for small pitch FinFET devices

Stacked Gate-All-Around FinFET and method forming the same

Integrated circuit structure with substrate isolation and un-doped channel

Method of forming a FinFET device

Semiconductor structure with recessed source/drain structure and method for forming the same

Multi-gate device and method of fabrication thereof

Multi-gate device and method of fabrication thereof

Wrap around silicide for FinFETs

Semiconductor structure with feature spacer and method for manufacturing the same

CHARTERED SEMICONDUCTOR MFG

Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection

Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials

Method to form a self-aligned CMOS inverter using vertical device integration

Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon

Method to form a self-aligned CMOS inverter using vertical device integration

Method for forming a transistor gate dielectric with high-K and low-K regions

Method to form a low parasitic capacitance pseudo-SOI CMOS device

Method for forming variable-K gate dielectric

Method to form and/or isolate vertical transistors

Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner

Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)

Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation

Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge

Method to form smaller channel with CMOS device by isotropic etching of the gate materials

Method for forming a lightly doped source and drain structure using an L-shaped spacer

Method to form CoSi2 on shallow junction by Si implantation

Method for forming a raised source and drain without using selective epitaxial growth