Wrap around silicide for FinFETs

Abstract

A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

What is claimed is: 
     
       1. A method comprising:
 forming a gate stack on a middle portion of a semiconductor fin; 
 forming a first gate spacer on a sidewall of the gate stack; 
 after the first gate spacer is formed, forming a template dielectric region to cover the semiconductor fin; 
 recessing the template dielectric region; 
 after the recessing, forming a second gate spacer on the sidewall of the gate stack; 
 etching an end portion of the semiconductor fin to form a recess in the template dielectric region; and 
 epitaxially growing a source/drain region in the recess. 
 
     
     
       2. The method of  claim 1 , wherein the first gate spacer and the second gate spacer are formed of different dielectric materials. 
     
     
       3. The method of  claim 2 , wherein the first gate spacer is formed of silicon carbo-nitride, and the second gate spacer is formed of silicon oxycarbo-nitride. 
     
     
       4. The method of  claim 1  further comprising:
 when the first gate spacer is formed on the sidewall of the gate stack, simultaneously forming a fin spacer on a sidewall of the end portion of the semiconductor fin; and 
 after the recess is formed, further etching the fin spacer to expand the recess, wherein the source/drain region is grown in the expanded recess. 
 
     
     
       5. The method of  claim 1  further comprising:
 after the recessing the template dielectric region, performing an oxidation on the first gate spacer, wherein a first portion of the first gate spacer over the template dielectric region is oxidized, and a second portion of the first gate spacer lower than a top surface of the template dielectric region is not oxidized. 
 
     
     
       6. The method of  claim 1  further comprising, after the source/drain region is formed, removing the template dielectric region. 
     
     
       7. The method of  claim 1  further comprising, after the source/drain region is formed, siliciding sidewalls of the source/drain region. 
     
     
       8. A method comprising:
 forming a gate stack on a middle portion of a semiconductor fin; 
 forming a first gate spacer on a sidewall of the gate stack; 
 after the first gate spacer is formed, forming a template dielectric region, with a top surface of the template dielectric region being substantially level with a top surface of the semiconductor fin; 
 etching an end portion of the semiconductor fin to form a recess in the template dielectric region; 
 epitaxially growing a source/drain region in the recess; 
 removing at least a portion of the template dielectric region to expose sidewalls of the source/drain region; and 
 siliciding the sidewalls of the source/drain region. 
 
     
     
       9. The method of  claim 8 , wherein the removing the template dielectric region comprises etching the template dielectric region until a portion of a dielectric layer overlapped by the template dielectric region is exposed, and wherein the dielectric layer is formed simultaneously as the first gate spacer. 
     
     
       10. The method of  claim 8  further comprising, after the template dielectric region is formed, forming a second gate spacer on a sidewall of the first gate spacer. 
     
     
       11. The method of  claim 10 , wherein the first gate spacer and the second gate spacer are formed of different dielectric materials. 
     
     
       12. The method of  claim 11 , wherein the first gate spacer is formed of silicon carbo-nitride, and the second gate spacer is formed of silicon oxycarbo-nitride. 
     
     
       13. The method of  claim 8  further comprising:
 when the first gate spacer is formed on the sidewall of the gate stack, simultaneously forming a fin spacer on a sidewall of the end portion of the semiconductor fin; and 
 after the recess is formed, further etching the fin spacer to expand the recess. 
 
     
     
       14. The method of  claim 8  further comprising:
 performing an oxidation on the first gate spacer, wherein a first portion of the first gate spacer over the template dielectric region is oxidized, and a second portion of the first gate spacer under a top surface of the template dielectric region is not oxidized. 
 
     
     
       15. The method of  claim 8  further comprising:
 increasing a k value of a first portion of the first gate spacer over the template dielectric region, and a k value of a second portion of the first gate spacer under a top surface of the template dielectric region remains unchanged. 
 
     
     
       16. A method comprising:
 forming a gate stack on a middle portion of a semiconductor fin; 
 forming a first gate spacer on a sidewall of the gate stack; 
 depositing a template dielectric region, with both the semiconductor fin and the first gate spacer being embedded in the template dielectric region; 
 etching back the template dielectric region to reveal the first gate spacer; 
 performing an oxidation on the first gate spacer to oxidize a top portion of the first gate spacer; 
 forming a second gate spacer on the sidewall of the gate stack; 
 etching an end portion of the semiconductor fin to form a recess in the template dielectric region; and 
 epitaxially growing a source/drain region in the recess. 
 
     
     
       17. The method of  claim 16 , wherein a lower portion of the first gate spacer is not oxidized by the oxidation. 
     
     
       18. The method of  claim 16 , wherein the first gate spacer and the second gate spacer are formed of different dielectric materials. 
     
     
       19. The method of  claim 18 , wherein the first gate spacer is formed of silicon carbo-nitride, and the second gate spacer is formed of silicon oxycarbo-nitride. 
     
     
       20. The method of  claim 16  further comprising:
 when the first gate spacer is formed on the sidewall of the gate stack, simultaneously forming a fin spacer on a sidewall of the end portion of the semiconductor fin; and 
 after the recess is formed, further etching the fin spacer to expand the recess, wherein the source/drain region is grown in the expanded recess.