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Inventor

STEVENS JEFFREY C

US24 patents
⚠️ This page may combine multiple inventors who share the name “STEVENS JEFFREY C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COMPAQ COMPUTER CORP

17 patents
US6286083B1Sep 4, 2001

Computer system with adaptive memory arbitration scheme

COMPAQ COMPUTER CORP213 citations98
US6247102B1Jun 12, 2001

Computer system employing memory controller and bridge interface permitting concurrent operation

COMPAQ COMPUTER CORP68 citations96
US5774680AJun 30, 1998

Interfacing direct memory access devices to a non-ISA bus

COMPAQ COMPUTER CORP31 citations96
US5446863AAug 29, 1995

Cache snoop latency prevention apparatus

COMPAQ COMPUTER CORP53 citations96
US5325503AJun 28, 1994

Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line

COMPAQ COMPUTER CORP107 citations96
US5813022ASep 22, 1998

Circuit for placing a cache memory into low power mode in response to special bus cycles executed on the bus

COMPAQ COMPUTER CORP56 citations95
US6226700B1May 1, 2001

Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices

COMPAQ COMPUTER CORP81 citations94
US5426765AJun 20, 1995

Multiprocessor cache abitration

COMPAQ COMPUTER CORP97 citations94
US5335335AAug 2, 1994

Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed

COMPAQ COMPUTER CORP103 citations94
US6088517AJul 11, 2000

Interfacing direct memory access devices to a non-ISA bus

COMPAQ COMPUTER CORP20 citations92
US6041401AMar 21, 2000

Computer system that places a cache memory into low power mode in response to special bus cycles executed on the bus

COMPAQ COMPUTER CORP27 citations92
US5778413AJul 7, 1998

Programmable memory controller having two level look-up for memory timing parameter

COMPAQ COMPUTER CORP49 citations92
US5724550AMar 3, 1998

Using an address pin as a snoop invalidate signal during snoop cycles

COMPAQ COMPUTER CORP21 citations92
US5793693AAug 11, 1998

Cache memory using unique burst counter circuitry and asynchronous interleaved RAM banks for zero wait state operation

COMPAQ COMPUTER CORP47 citations91
US6101566AAug 8, 2000

Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices

COMPAQ COMPUTER CORP34 citations90
US5781925AJul 14, 1998

Method of preventing cache corruption during microprocessor pipelined burst operations

COMPAQ COMPUTER CORP8 citations74
US5617557AApr 1, 1997

Using an address pin as a snoop invalidate signal during snoop cycles

COMPAQ COMPUTER CORP4 citations63

HEWLETT PACKARD DEVELOPMENT CO

5 patents

COMPAQ INFORMATION TECHNOLOGIE

1 patent

BROOKS ROBERT C

1 patent