Inventor

MOR YI-SHIEN

TW39 patents

⚠️ This page may combine multiple inventors who share the name “MOR YI-SHIEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOR YI-SHIEN

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of forming a single metal that performs N work function and P work function in a high-k/metal gate process

Integrated high-K/metal gate in CMOS process flow

Control fin heights in FinFET structures

Fin critical dimension loading optimization

Method for fabricating semiconductor device including contact bars having narrower portions

Semiconductor device having a contact bar over an S/D structure

Fin critical dimension loading optimization

Gate stacks for semiconductor devices of different conductivity types

Semiconductor device and a method for fabricating the same

Single metal that performs N work function and P work function in a high-K/metal gate

Semiconductor device and method of forming semiconductor fin thereof

Integrated circuit structure

Method of forming semiconductor structure

Gate-top dielectric structure for self-aligned contact

Semiconductor structure and manufacturing method thereof

Method of making a structure

TAIWAN SEMICONDUCTOR MFG

Integrated high-K/metal gate in CMOS process flow

Semiconductor devices with dual-metal gate structures and fabrication methods thereof

Integrated high-k/metal gate in CMOS process flow

High-k metal gate CMOS patterning method

Spacer shape engineering for void-free gap-filling process

Method of integrating high-K/metal gate in CMOS process flow

Control fin heights in FinFET structures

Integrated high-k/metal gate in CMOS process flow

Method for forming silicide and semiconductor device formed thereby

Semiconductor devices with dual-metal gate structures and fabrication methods thereof

UNITED MICROELECTRONICS CORP

Method of repairing a low dielectric constant material layer

Air gap semiconductor structure and method of manufacture

Air gap semiconductor structure and method of manufacture

Method of avoiding dielectric layer deterioration with a low dielectric constant

Air gap semiconductor structure and method of manufacture

Post-processing treatment of low dielectric constant material

Method of avoiding dielectric layer deterioation with a low dielectric constant during a stripping process

MOR YI-SHIEN

FinFETs and methods for forming the same

FinFET design with LDD extensions

Control fin heights in FinFET structures

LIN YIH-ANN

Method of forming a single metal that performs N work function and P work function in a high-k/metal gate process

WU MING-YUAN

Spacer shape engineering for void-free gap-filling process

LIU CHIA-CHU

Semiconductors structure with elements having different widths and methods of making the same