Gate stacks for semiconductor devices of different conductivity types

Abstract

A semiconductor device includes a semiconductor substrate, an isolation structure in the semiconductor substrate for isolating a first active region and a second active region, a first device formed in the first active region, and a second device formed in the second active region. The first device has a first gate dielectric layer and a first gate electrode over the first gate dielectric layer. The first gate electrode includes at least one of Ta and C, and has a first work function for a first conductivity. The second device has a second gate dielectric layer and a second gate electrode over the second gate dielectric layer. The second gate electrode includes at least one of Ta, C, and Al, and has a second work function for a second conductivity. The second conductivity is different from the first conductivity.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a semiconductor substrate; 
 a first active region and a second active region in the semiconductor substrate; 
 a first device formed in the first active region, the first device having a first gate dielectric layer and a first gate electrode, wherein the first gate electrode has a first work function for a first conductivity; and 
 a second device formed in the second active region, the second device having a second gate dielectric layer and a second gate electrode, wherein the second gate electrode has a second work function and includes Al at a concentration such the second gate electrode has a second conductivity opposite from the first conductivity, wherein the first gate electrode and second gate electrodes are formed from first and second portions of a material layer, respectively, wherein the first portion of the material layer is not treated with an Al implantation process and the second portion of the material layer is treated with an Al implantation process. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the first work function is an N-metal work function and the second work function is a P-metal work function. 
     
     
       3. The semiconductor device of  claim 1 , wherein the first gate electrode includes TaC. 
     
     
       4. The semiconductor device of  claim 1 , wherein the first and second gate dielectric layers includes one of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium oxide (HMO), hafnium zirconium oxide (HfZrO), and combinations thereof. 
     
     
       5. The semiconductor device of  claim 1 , wherein the first and second devices each includes a capping layer and the capping layers comprise lanthanum oxide and aluminum oxide. 
     
     
       6. The semiconductor device of  claim 1 , wherein the first device further includes an interfacial layer under the first gate dielectric layer. 
     
     
       7. The semiconductor device of  claim 6 ,
 wherein the first active region is isolated from the second active region by an isolation structure, 
 wherein the interfacial layer and the isolation structure are spaced apart. 
 
     
     
       8. A semiconductor device comprising:
 a semiconductor substrate having a first active region and a second active region; 
 an isolation structure isolating the first and second active regions; 
 a first gate stack in the first active region, the first gate stack having a first high-k gate dielectric layer and a first gate electrode layer, wherein the first gate electrode layer has a first work function for a first conductivity; and 
 a second gate stack in the second active region, the second gate stack having a second high-k gate dielectric layer and a second gate electrode layer, wherein the second gate electrode layer has a second work function and includes Al at a concentration such that the second gate electrode layer has a second conductivity that is opposite from the first conductivity, wherein the first gate electrode layer is formed from a first portion of a material layer that is not treated with an Al implantation process, wherein the second gate electrode layer is formed from a second portion of the material layer after being treated with the Al implantation process. 
 
     
     
       9. The semiconductor device of  claim 8 , wherein the first gate electrode layer and the second gate electrode layer include about the same Ta contents and about the same C contents. 
     
     
       10. The semiconductor device of  claim 9 , wherein the Al contents in the second gate electrode layer is introduced by ion implantation. 
     
     
       11. The semiconductor device of  claim 8 , wherein the second work function is greater than the first work function. 
     
     
       12. The semiconductor device of  claim 8 , wherein each of the first and second high-k gate dielectric layers includes hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or a combination thereof. 
     
     
       13. The semiconductor device of  claim 8 , wherein the first gate stack further includes an interfacial layer under the first high-k gate dielectric layer, and the second gate stack further includes the interfacial layer under the second high-k gate dielectric layer. 
     
     
       14. The semiconductor device of  claim 8 , wherein the first gate stack further includes a poly layer over the first gate electrode layer, and the second gate stack further includes the poly layer over the second gate electrode layer. 
     
     
       15. A semiconductor device comprising:
 a semiconductor substrate having a first region and a second region; 
 a first gate stack in the first region, the first gate stack having a first high-k gate dielectric layer and a first work function layer, wherein the first work function layer has a first work function for a first conductivity; and 
 a second gate stack in the second region, the second gate stack having a second high-k gate dielectric layer and a second work function layer, wherein the second work function layer has a second work function and has a second conductivity that is opposite the first conductivity, wherein the first work function layer is formed from a first portion of a TaC layer that is not treated with an Al implantation process, wherein the second work function layer is formed from a second portion of the TaC layer after being treated with the Al implantation process. 
 
     
     
       16. The semiconductor device of  claim 15 , wherein the first and second work function layers have about the same TaC contents. 
     
     
       17. The semiconductor device of  claim 15 , wherein the Al contents in the second work function layer are introduced by ion implantation. 
     
     
       18. The semiconductor device of  claim 15 , wherein the Al contents in the second work function layer are introduced by plasma treatment. 
     
     
       19. The semiconductor device of  claim 15 , wherein each of the first and second gate stacks further includes an interfacial layer under the first and second high-k gate dielectric layers, respectively. 
     
     
       20. The semiconductor device of  claim 15 , wherein the first and second work function layers have about the same height.